Abstract: An analog to digital converter comprising at least one sampling capacitor connected to a sample node, and a pre-charge circuit arranged to cause the voltage on the sample node to substantially match the input voltage prior to the analog to digital converter entering an acquire mode in which the sample node is connected to the input node by a sample switch.

Abstract: In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

Abstract: Systems and methods to determine locations for dual touch operations performed on a four-wire resistive touch screen. The systems and methods may include measuring signals from pairs of electrodes on each of a first and second resistive sheet of the resistive touch screen in two phases of operation. The systems and methods may further include determining touch screen segment resistances from the signal measurements. The systems and methods may determine locations corresponding to the dual touch operations from the resistances. The systems and methods may also determine locations from the signal measurements.

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Abstract: Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Abstract: A receiver architecture for processing spread spectrum signals. The receiver has an RF front end to receive and down convert a broadcast signal to an intermediate frequency carrier. The IF signal is digitized and provided to a processor (which may be a software-driven DSP, an ASIC or other embodiment) for processing. A given IF carrier is removed and the signal is low pass filtered. The signal is provided to a number of channels, each, for example, correspond to a unique transmitter. On each channel the sample rate is reduced to a predetermined fixed rate with timing mismatch compensated. The Doppler frequency shift, as estimated for the channel, is removed succeedingly. A locally generated copy of the spreading code used by the transmitter is applied to the carrier and Doppler removed signal at the predetermined fixed sample rate. The de-spread signal is used to provide estimates of the Doppler shift and for subsequent sample selection.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.

Abstract: An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening.

Abstract: Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.

Abstract: An amplifier system may include a power stage having inputs for three different supply voltages and an output for coupling to a load, a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels, a monitor to provide a first control signal to the controller based on an input voltage signal, and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal.

Abstract: The present disclosure proposes a fully integrated accurate LED output current controlling circuit and method, which can be seamlessly combined with true PWM dimming. The current controlling circuit has an auto zero function in the light-emitting diode driver to eliminate offsets caused by the system, process variations, parasitic effects, dimming and so on in an LED driver application, and thus is capable of controlling the LED current with high accuracy. Moreover, the driver of the present disclosure does not require the use of external components such as an external resistor to regulate current accuracy.

Abstract: Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.

Abstract: A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract: A system architecture allows for the transmission of multiple HDCP encrypted audio/video streams over a single unified cable to multiple receivers using a daisy chain topology. Each individual audio/video stream is first encrypted and then combined into a uniform stream, and the uniform stream is transmitted to each of the receivers. Each receiver contains a decryption engine that operates independently of the engines in the other receivers, therefore allowing each receiver to select to a unique channel and decrypt and display one of the audio/video streams.