Abstract: Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p?p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p?p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.

Abstract: Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error.

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.

Abstract: Methods and apparatus automatically cancel or attenuate an unwanted signal (such as low frequencies from wind buffets) from, and/or control frequency response of, a condenser microphone, or control the effective condenser microphone sensitivity before the signal reaches an ASIC or other processing circuit. As a result, the maximum amplitude signal seen by the processing circuit is limited, thereby preventing overloading the input of the processing circuit. Remaining (wanted) frequencies can be appropriately amplified to reduce the noise burden on further processing circuits. A corrective signal is applied to a bias terminal of the condenser microphone to cancel the unwanted signal. Optionally or alternatively, a controllable impedance is connected to a line that carries the signal generated by the MEMS microphone, so as to attenuate unwanted portions of the signal.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: Apparatus and methods reduce increase the common mode range of a difference amplifier. A circuit uses one or more floating powers and one or more floating grounds coupled to an input stage of an amplifier to increase the common mode range of a difference amplifier. The floating power can be configured to select from the greater of the voltage level of one of the differential signals and the system power high source. The floating ground can be configured to select from the lesser of the voltage level of one of the differential signals and the system power low source.

Abstract: A method according to an embodiment of a system for efficient resource management of a signal flow programmed digital signal processor code is provided and includes determining a connection sequence of a plurality of algorithm elements in a schematic of a signal flow for an electronic circuit, the connection sequence indicating connections between the algorithm elements and a sequence of processing the algorithm elements according to the connections, determining a buffer sequence indicating an order of using the plurality of memory buffers to process the plurality of algorithm elements according to the connection sequence, and reusing at least some of the plurality of memory buffers according to the buffer sequence.

Abstract: Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Abstract: A power-efficient, rail-to-rail input circuit includes two differential pairs, one having devices of a first threshold voltage and one having devices of a second, different threshold voltage. In various embodiments, the two differential pairs receive a differential input in parallel and are supplied a tail current, which a control circuit steers between the pairs in accordance with a common-mode level of the input.

Abstract: Error sources related to aerodynamics of an inertial sensor resonator are detected by modulating the distance between the resonator and the underlying substrate and sensing modulated error signals in the accelerometer that are induced by such modulation. Compensating signals may be provided to substantially cancel errors caused by such error sources.

Abstract: A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods.

Abstract: Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract: A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.

Abstract: An approach to signal conversion adapts the signal conversion process, for example, by adapting or configuring signal conversion circuitry, according to inferred characteristics (e.g., probability distribution of value) of a signal being converted. As an example, an analog-to-digital converter (ADC) may be adapted so that its accuracy varies across the range of possible input signal values in such a way that on average the digital signal provides a higher accuracy than had the accuracy remained fixed. In another example, models (and corresponding inference circuitry) of both an input signal process and of a quantization process are used to improve signal conversion accuracy.

Abstract: Amplifiers with voltage and current feedback error correction are provided. In one embodiment, an amplifier includes a first input terminal, a second input terminal, an output terminal, a first stage, and a voltage feedback amplification circuit. The first stage can be used to generate first and second output currents, which can be used to control a voltage level of the output terminal. The first and second output currents can change in response to a current feedback signal and a differential input signal received between the first and second input terminals. The first stage can also generate a voltage feedback signal, which can be used by the voltage feedback amplification circuit to control a voltage level of the second input terminal based on a voltage level of the first input terminal.