Abstract: A LED drive system for controlling an off-chip power supply enables the power supply function to be located ‘off-chip’—i.e., on an IC which is separate from the IC containing the other LED drive system components. The off-chip supply provides a common line voltage for LED strings connected in series with respective current sink circuits at respective junctions, in response to a signal applied to a control input. The system includes a ‘minimum’ circuit which outputs the least of the voltages at the junctions, and an I/O pin which receives a signal that varies with the output of the minimum circuit. When the external supply's control input is coupled to the system's I/O pin, the present system controls the output of the external power supply as needed to provide a desired common line voltage.

Abstract: Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter.

Abstract: A bias voltage source for a differential circuit has low output impedance at DC, but considerably higher output impedance within the frequency band of the differential signal being processed, to provide an accurate, well-matched common-mode bias voltage to each component of a differential signal path, while providing a low noise current, minimizing the conversion between common-mode and differential modes, and preserving available headroom, and all without requiring the use of large resistors.

Abstract: A redundant analog-to-digital conversion system can include at least one input multiplexer, first and second redundant analog-to-digital converters, a comparison circuit and an output multiplexer. The at least one input multiplexer can receive a plurality of analog input signals and output at lest one multiplexed analog input signal. The first and second redundant analog-to-digital converters can convert the at least one multiplexed analog input signal to respectively generate first and second digital output signals, the first digital output having a greater digital resolution than the second digital output. The comparison circuit can produce a comparison output signal as a function of a comparison of a plurality of most significant corresponding bit pairs of the first and second digital output signals. The output multiplexer can produce a multiplexed output including information from the comparison output signal and one of the digital output signals.

Abstract: An auto-zero amplifier includes a main amplifier for amplifying an input signal; the main amplifier receives an offset-correction signal for cancelling an offset at a first common-mode level of the input signal. At the first common-mode level, the offset-correction signal is based on a first value stored using a first offset-storage element. When a change is detected in the input common-mode from the first level to a second level, the first offset-storage element is switched out and a second offset-storage element, having a second value based on the second common-mode level, is switched in.

Abstract: The proper operation of a phase locked loop is determined by monitoring certain signals within the loop for their phase relationship or duty cycle. If a malfunction of the loop is detected, proper operation may be imposed or restored by resetting a phase-frequency detector, or by flipping the output of the phase-frequency detector.

Abstract: A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures to reduce package vibration, reduce die stress, increase vertical mount stability, and improve solder joint reliability. The vertical mount package includes a first leadframe having first leads and molding material substantially surrounding at least a portion of the first leads. The molding material forms a cavity for holding the MEMS sensor and forms a package mounting plane for mounting the package on a base. The cavity has a die mounting plane that is substantially non-parallel to the package mounting plane. The first leads are configured to provide electrical contacts within the cavity and to provide electrical contacts to the base.

Abstract: The process of implementing a belief propagation network in software and/or hardware can begin with a factor-graph-designer who designs a factor graph that implements that network. A development system provides a user with a way to specify a factor graph at a high or abstract level, and then solve the factor graph, or make an instance of the factor graph in software and/or hardware based on the specification. Factor graphs enable designers to create a graphical model of complicated belief propagation networks such as Markov chains, hidden Markov models, and Bayesian networks.

Abstract: The present invention relates to a switched mode voltage regulator circuit comprising a regulation loop coupled between the output voltage of the regulator and a switch driver. The regulation loop comprising an error signal generator supplying a digital error signal representative of a voltage difference between the output voltage and a reference voltage. The regulation loop further comprises a linear digital filter and a non-linear digital filter both coupled for receipt of the digital error signal and a digital summer coupled for receipt of linearly and non-linearly filtered digital error signals to provide a combined digital error signal. A digital pulse modulator is configured to generate the pulse width or pulse density modulated driver control signal in accordance with the combined digital error signal.

Abstract: Embodiments of the present invention may provide string DAC architecture with multiple stages for efficient resolution extension. A first stage may include an impedance string (e.g., resistor string). A second stage may include a switch network with each switch having more than two states (impedance values). A third stage may include a string DAC with an impedance string with a set of corresponding switches. In multi-channel embodiments, multiple second and third stages may be provided for each channel while sharing the same first stage (i.e., impedance string). Each second stage switch networks may be controlled based on the relationship between the different channels such as MSB values. Thus, the second stage switch networks may provide different impedance values to compensate for loading effects in multi-channel, multi-stage string DAC designs.

Abstract: Loop instructions are analyzed and assigned stage numbers based on dependencies between them and machine resources available. The loop instructions are selectively executed based on their stage numbers, thereby eliminating the need for explicit loop set-up and tear-down instructions. On a Single Instruction, Multiple Data machine, the final instance of each instruction may be executed on a subset of the processing elements or vector elements, dependent on the number of iterations of the original loop.

Abstract: A method for producing a MEMS device having improved charge elimination characteristics includes providing a substrate having one or more layers, and applying a first charge elimination layer onto at least one portion of one given layer of the substrate. The method may then (1) apply a sacrificial layer onto the first charge elimination layer, (2) apply a second charge elimination layer onto at least a portion of the sacrificial layer, and (3) deposit a movable layer onto at least a portion of the second charge elimination layer. To form a structure within the movable layer the method may etch the movable layer. The method may then etch the sacrificial layer to release the structure.

Abstract: In an inertial sensor having a resonator and an accelerometer, acceleration signals are induced by resonating at least one shuttle of the resonator in a device plane at a shuttle resonance mode frequency and modulating the motion of the at least one resonator shuttle to induce accelerometer signals from the accelerometer. The motion may be modulated in the device plane or out of the device plane. A shuttle resonance mode and an accelerometer resonance mode may me matched based on the induced accelerometer signals, for example, by providing a feedback signal to the inertial sensor in response to such induced accelerometer signals to substantially nullify the induced accelerometer signals.

Abstract: A bulk acoustic wave gyroscope has a primary member in a member plane, and an electrode layer in an electrode plane spaced from the member plane. The electrode layer has a first portion that is electrically isolated from a second portion. The first portion, however, is mechanically coupled with the second portion and faces the primary member (e.g., to actuate or sense movement of the primary member). For support, the second portion of the electrode is directly coupled with structure in the member plane.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: Controlling the output voltage of a power supply involve determining a remote load coupled to the power supply and setting the output voltage based on the determined remote load and a predetermined maximum current for the power supply. The remote load may be measured, for example, by applying a predetermined current to the load, measuring the voltage across the load, and computing the effective load (resistance) value based on the supplied current and the measured voltage. Such measurement may be done using an analog-to-digital converter.

Abstract: Voltage regulator structures and methods embodiments are provided which employ a high-side N-type switching transistor to thereby enhance system efficiency and also reduce the die area required by these regulator structures. This structure and its advantages, however, require a gate drive signal higher than the input voltage of the voltage regulator. The embodiments resolve this need with a bias capacitor in a bootstrapped arrangement and a control loop arranged to maintain a bias voltage across the capacitor sufficient to always insure rapid switching of the high-side switching transistor during a pulse-width modulation (PWM) operational mode. The embodiments further include a second control loop arranged to insure sufficient voltage across the capacitor during a pulse-frequency modulation (PFM) operational mode.

Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.

Abstract: An apparatus and method for determining characterizing attributes of an actuator is provided. An actuator may be moved to a maximum capacitance position. At the maximum capacitance position, an initial measurement of the actuator capacitance is made. The actuator is moved a predetermined increment toward a first extreme position, and the actuator capacitance is again measured. If the capacitance changed by a threshold amount, the signal preceding the signal that caused the actuator to move is recorded as an approximate response curve end point, or the first extreme position. The actuator is again moved a predetermined increment toward a second extreme position. After each move, the capacitance is measured. If it is determined the capacitance did change by a threshold amount from the previously measured capacitance, the signal related to the previously measured capacitance is recorded as an approximate response curve end point, or the second extreme position.

Abstract: In a teeter-totter type MEMS accelerometer, the teeter-totter proof mass and the bottom set of electrodes (i.e., underlying the proof mass) are formed on a device wafer, while the top set of electrodes (i.e., overlying the teeter-totter proof mass) are formed on a circuit wafer that is bonded to the device wafer such that the top set of electrodes overlie the teeter-totter proof mass. The electrodes formed on the circuit wafer may be formed from an upper metallization layer on the circuit wafer, which also may be used to form various electrical connections and/or bond pads.