Patents Assigned to Analog Devices
  • Patent number: 11712516
    Abstract: A substance delivery device is disclosed. The substance delivery device includes a lever that includes a drive arm that is rotatable about a pivot. The substance delivery device also includes a pump that has a deformable chamber. The deformable chamber is configured to rotate the drive arm about the pivot towards a container so as to deform the container to drive a fluid substance from the container.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: August 1, 2023
    Assignee: Analog Devices, Inc.
    Inventors: David Frank Bolognia, Brian Hall
  • Publication number: 20230234835
    Abstract: Packaging of microfabricated devices, such as integrated circuits, microelectromechanical systems (MEMS), or sensor devices is described. The packaging is 3D heterogeneous packaging in at least some embodiments. The 3D heterogeneous packaging includes an interposer. The interposer includes stress relief platforms. Thus, stresses originating in the packaging do not propagate to the packaged device. A stress isolation platform is an example of a stress relief feature. A stress isolation platform includes a portion of an interposer coupled to the remainder of the interposer via stress isolation suspensions. Stress isolation suspensions can be formed by etching trenches through the interposer.
    Type: Application
    Filed: January 24, 2023
    Publication date: July 27, 2023
    Applicant: Analog Devices, Inc.
    Inventors: Xin Zhang, Jianglong Zhang, Li Chen, John C. Cowles, Michael Judy, Shafi Saiyed
  • Patent number: 11711200
    Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: July 25, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Michael St. Germain, John Kenney
  • Patent number: 11711094
    Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: July 25, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventor: Mahesh Madhavan Kumbaranthodiyil
  • Patent number: 11711085
    Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: July 25, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Alexander Leonard, Lu Wu, Christopher Mayer, Gord Allan
  • Patent number: 11711073
    Abstract: A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: July 25, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Andrew Joseph Thomas
  • Patent number: 11711894
    Abstract: Isolators for high frequency signals transmitted between two circuits configured to operate at different voltage domains are provided. The isolators may include resonators capable of operating at high frequencies with high bandwidth, high transfer efficiency, high isolation rating, and a small substrate footprint. In some embodiments, the isolators may operate at a frequency not less than 30 GHz, not less than 60 GHz, or between 20 GHz and 200 GHz, including any value or range of values within such range. The isolators may include isolator components galvanically isolated from and capacitively coupled to each other. The sizes and shapes of the isolator components may be configured to control the values of equivalent inductances and capacitances of the isolators to facilitate resonance in operation. The isolators are compatible to different fabrication processes including, for example, micro-fabrication and PCB manufacture processes.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: July 25, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Jinglin Xu, Paul Lambkin, Ramji Lakshmanan, Baoxing Chen
  • Patent number: 11709235
    Abstract: Techniques to adjust a gain of an analog-to-digital converter circuit (ADC) and/or an ADC full scale from one sample to the next of an analog input signal to compensate for the signal loss over distance, which can increase an effective dynamic range of the system. The benefit of compensating for the signal loss due to distance is that a data interface between the ADC of the receiver of the LIDAR system and a signal processor no longer needs to support the dynamic range from the range specification.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 25, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Shawn S. Kuo, Lijun Gao
  • Publication number: 20230228888
    Abstract: One embodiment is a method for counting charge events detected by a pixel in a photon-counting computed tomography (PCCT) scanning system comprising a plurality of discriminators, wherein each discriminator is associated with a respective one of a plurality of threshold voltage levels. The method includes detecting a signal output from one of the discriminators; incrementing a quantitative count corresponding to the threshold voltage level associated with the one of the discriminators if the detected discriminator output signal meets a first condition; and incrementing a qualitative count if the detected discriminator output signal meets at least one second condition.
    Type: Application
    Filed: December 13, 2022
    Publication date: July 20, 2023
    Applicant: Analog Devices, Inc.
    Inventors: Patrick S. RIEHL, Sunrita PODDAR
  • Publication number: 20230231569
    Abstract: Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Applicant: Analog Devices International Unlimited Company
    Inventors: Daniel H. SAARI, Lewis F. LAHR
  • Patent number: 11705914
    Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: July 18, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Reuben P. Nelson
  • Patent number: 11702335
    Abstract: An integrated device package is disclosed. The integrated device package can include a package housing that defines a cavity. The integrated device package can include an integrated device die that is disposed in the cavity. The integrated device die has a first surface includes a sensitive component. A second surface is free from a die attach material. The second surface is opposite the first surface. The integrated device die include a die cap that is bonded to the first surface. The integrated device package can also include a supporting structure that attaches the die cap to the package housing.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 18, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Yeonsung Kim, Shafi Saiyed, Thomas M. Goida
  • Publication number: 20230224639
    Abstract: Systems, devices, and methods related to audio systems for providing personalized audio zones are provided. An example audio system includes a first speaker to transmit an ultrasonic signal modulated by a first portion of a first audio signal. The audio system further includes a second speaker to transmit a second portion of the first audio signal, where the second portion is in a lower frequency band than the first portion. The audio system further includes a noise canceller to at least attenuate a second audio signal, where the second audio signal is in a lower frequency band than the first portion of the first audio signal.
    Type: Application
    Filed: December 19, 2022
    Publication date: July 13, 2023
    Applicant: Analog Devices, Inc.
    Inventors: Boris LERNER, Gina G. AQUILANO
  • Patent number: 11697882
    Abstract: Various examples are directed to a solar power electrolyzer system comprising a first electrolyzer stack, a second electrolyzer stack, a first converter and a first converter controller. The first electrolyzer stack may be electrically coupled in series with a photovoltaic array. The first converter may be electrically coupled in series with the first electrolyzer stack and electrically coupled in series with the photovoltaic array. The second electrolyzer stack electrically may be coupled at an output of the first converter. The first converter controller may be configured to control a current gain of the first converter.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: July 11, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Brian Harrington, Leonard Shtargot, Antonio Montalvo
  • Patent number: 11698257
    Abstract: According to some aspects, there is provided a microelectromechanical systems (MEMS) device wherein one or more components of the MEMS device exhibit attenuated motion relative to one or more other moving components. The MEMS device may comprise a substrate; a proof mass coupled to the substrate and configured to move along a resonator axis; and a first shuttle coupled to the proof mass and comprising one of a drive structure configured to drive the proof mass along the resonator axis or a sense structure configured to move along a second axis substantially perpendicular to the resonator axis in response to motion of the proof mass along the resonator axis, wherein displacement of at least a first portion of the proof mass is attenuated relative to displacement of the first shuttle and/or a second portion of the proof mass.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: July 11, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Igor P. Prikhodko, John A. Geen
  • Publication number: 20230213468
    Abstract: A reference electrode with a liquid-impermeable enclosure comprises a chamber for a reference electrolyte. The reference electrode also comprises a first electrode element comprises a reference electrolyte electrode surface arranged to contact a reference electrolyte located within the chamber and a second electrode element is provided at least partially outside the enclosure and comprises a sample electrode surface for contacting a sample. The first and second electrode are electrically connected through the enclosure. Alternatively or additionally, a conductive connecting element defining a part of the enclosure and/or extending through the enclosure electrically connects the first electrode element and the second electrode element.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Applicant: Analog Devices International Unlimited Company
    Inventors: Youri Victorvitch PONOMAREV, Alfonso BERDUQUE
  • Patent number: 11695093
    Abstract: A device emitting mid-infrared light that comprises a semiconductor substrate of GaSb or closely related material. The device can also comprise epitaxial heterostructures of InAs, GaAs, AlSb, and related alloys forming light emitting structures cascaded by tunnel junctions. Further, the device can comprise light emission from the front, epitaxial side of the substrate.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 4, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Shrenik Deliwala, Ryan Michael Iutzi
  • Patent number: 11695070
    Abstract: A power device can be structured with a power switch having multiple arrangements such that the power switch can operate as a power switch with the capability to measure properties of the power switch. An example power device can comprise a main arrangement of transistor cells and a sensor arrangement of sensor transistor cells. The main arrangement can be structured to operate as a power switch, with the transistor cells of the main arrangement having control nodes connected in parallel to receive a common control signal. The sensor arrangement of sensor transistor cells can be structured to measure one or more parameters of the main arrangement, with the sensor transistor cells having sensor control nodes connected in parallel to receive a common sensor control signal. The sensor transistor cells can have a common transistor terminal shared with a common transistor terminal of the transistor cells of the main arrangement.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: July 4, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventor: Bernhard Strzalkowski
  • Patent number: 11695330
    Abstract: A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 4, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Ciaran Brennan, Brian K. Jadus, Keith W. Bennett
  • Patent number: 11692825
    Abstract: A MEMS device is provided comprising a mass configured to move along a first axis and a second axis substantially perpendicular to the first axis; a drive structure coupled to the mass and configured to cause the mass to move along the first axis; a sense structure coupled to the mass and configured to detect motion of the mass along the second axis; a stress relief structure coupled to one of the drive structure or the sense structure; and at least one anchor coupled to an underlying substrate of the MEMS device, wherein the stress relief structure is coupled to the at least one anchor and the at least one anchor is disposed outside of the stress relief structure.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: July 4, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Gaurav Vohra