Patents Assigned to Analog Devices
  • Publication number: 20210297087
    Abstract: Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Applicant: Analog Devices, Inc.
    Inventor: Abhishek BANDYOPADHYAY
  • Publication number: 20210297100
    Abstract: Systems and methods are provided for optimizing offset compensation in a receiver with multiple offset compensation D/A converters. At each stage where offset cancellation is applied, there is a fan-out of two or more. At the final stage, comparator offset compensation codes are summed and compared against a digital reference. In one version the digital reference is zero. A second implementation has a non-zero digital reference which is the sum of comparator offsets stored from start up. The difference between the sum of offsets and digital reference is applied to a digital accumulator. The most significant bits of the digital accumulator are applied to a digital D/A converter, which cancel analog offsets in an intermediate stage of amplifiers. The summation of offsets feeding into an accumulator is implemented for all preceding stages.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 23, 2021
    Applicant: Analog Devices, Inc.
    Inventors: John KENNEY, Robert SCHELL, Rahul VEMURI
  • Publication number: 20210293535
    Abstract: Aspects of the embodiments are directed to non-contact systems, methods and devices for optical detection of objects in space at precise angles. This method involves the design and fabrication of photodiode arrays for measuring angular response using self-aligned Schottky platinum silicide (PtSi) PIN photodiodes (PN-diodes with an intrinsic layer sandwiched in between) that provide linear angular measurements from incident light in multiple dimensions. A self-aligned device is defined as one in which is not sensitive to photomask layer registrations. This design eliminates device offset between “left” and right” channels for normal incident light as compared to more conventional PIN diode constructions.
    Type: Application
    Filed: March 22, 2020
    Publication date: September 23, 2021
    Applicant: ANALOG DEVICES, INC.
    Inventors: Shrenik DELIWALA, Paul W. STEVENS, William Edward O'MARA
  • Patent number: 11128310
    Abstract: Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches and/or errors. The mismatches and/or errors can degrade the quality of the analog output. To extract the mismatches and/or errors, a transparent dither can be used. The mismatches and/or errors can be extracted by observing the analog output, and performing a cross-correlation of the observed output with a switching bit stream of the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the respective mismatches and/or errors.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: September 21, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Jialin Zhao, Hajime Shibata, Gil Engel, Yunzhi Dong
  • Patent number: 11125784
    Abstract: The response of a Rogowski coil based current measuring circuit is often proportional to frequency. To correct for this a low pass or integrating function is applied to the response to linearize it. The low pass filter is made from real resistors and capacitors, and tolerances in their values significantly affect the estimate of current. This disclosure relates to a way of addressing such problems. This allows consumers of electricity to have confidence in the accuracy of, for example, their electricity meter.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: September 21, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: Jonathan Ephraim David Hurwitz
  • Patent number: 11125817
    Abstract: A test system can use first and different second driver stages to provide test signals to a device under test (DUT). A compound stage can receive signals from the driver stages and provide a voltage output signal to the DUT, such as via a gain circuit. The compound stage can include a buffer circuit configured to provide a first portion of the voltage output signal based on a first output signal from the first driver stage, and the compound stage can include a transimpedance circuit configured to provide a second portion of the voltage output signal based on a second output signal from the second driver stage. In an example, the gain circuit can receive a superposition signal comprising the first and second portions of the voltage output signal and, in response, provide a test signal to the DUT.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 21, 2021
    Assignee: Analog Devices, Inc.
    Inventor: Christopher C. McQuilkin
  • Patent number: 11128287
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 21, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Patent number: 11127716
    Abstract: An integrated device package is disclosed. The package can include a carrier and an integrated device die having a front side and a back side. A mounting structure can serve to mount the back side of the integrated device die to the carrier. The mounting structure can comprise a first layer over the carrier and a second element between the back side of the integrated device die and the first layer. The first layer can comprise a first insulating material that adheres to the carrier, and the second element can comprise a second insulating material.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 21, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Rigan McGeehan, Cillian Burke, Alan J. O'Donnell
  • Patent number: 11119143
    Abstract: A device and method for measuring the internal impedance of an electronic sensor uses configurable gain stages to selectively apply different excitation signals to the sensor under test in order to ensure adequate signal-to-noise ratio to provide accurate measurement of the internal impedance over a broader range of internal impedances than the prior art.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 14, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: GuangYang Qu, Yincai Tony Liu, Baotian Hao, Hanqing Wang, Hengfang Mei, Rengui Luo, Yimiao Zhao, Junbiao Ding
  • Patent number: 11121718
    Abstract: Techniques to implement subtractive dither in a multi-stage ADC. Subtractive dither involves adding a first dither signal at a first node and adding a second dither signal at a second node (which can be the same as the first node), where the first and second dither signal combine and sum to approximately zero. By utilizing subtractive dither in a multi-stage ADC, the headroom requirements of a loop filter in a main loop of the ADC and the range requirements of a feedback DAC in the main loop can both be relaxed.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 14, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: Roberto Sergio Matteo Maurino
  • Patent number: 11121547
    Abstract: The present disclosure provides a method and device for overvoltage protection. Specifically, the present disclosure provides an overvoltage protection device which provides a feedback loop for electronic components such as amplifiers and digital to analog converters which require feedback. The overvoltage protection device also includes overvoltage switches in both the signal and feedback channels, which may be opened by a fault detector in the event of an overvoltage. The device also includes an overvoltage feedback channel coupled between the signal and feedback channels, and which also includes a switch which may be closed in the event of an overvoltage event. As such, the overvoltage device provides a closed loop feedback channel during an overvoltage event.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 14, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Alan Kelly, David Aherne, Aidan J. Cahalane
  • Patent number: 11121713
    Abstract: An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: ANALOG DEVICES, INC.
    Inventors: Scott G. Bardsley, Huseyin Dinc
  • Patent number: 11120940
    Abstract: For near field communications, inductive coils coupled to each communicating circuit are brought close together so that there is inductive coupling between the two coils. Data signals can then be relayed between the two circuits without any direct connection between them. However, the system is susceptible to common mode noise, such as ambient EMI. In addition to the “active” coil pairs used for transmitting and receiving data, a pair of “passive” coils is provided, proximate to the active coil pairs, that is only used for detecting the ambient EMI. The EMI signals detected by the passive coils are processed by a noise detector/processor, and the noise detector processor then controls the transmitters and/or receivers to at least partially compensate for the detected EMI signals. Transmit power or receiver thresholds may be controlled by the noise detector/processor to improve the signal-to-noise ratio, or other compensation techniques can be used.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 14, 2021
    Assignee: Analog Devices, Inc.
    Inventor: Kenneth G. Richardson
  • Patent number: 11121892
    Abstract: Various examples are directed to isolated analog-to-digital converter (ADC) circuits comprising a first side that is separated from a second side by an isolator. A first ADC positioned on the first side may be configured to convert a first analog input signal to a first side multi-bit digital signal. A digital modulator on the first side may be configured to convert the first side multi-bit digital signal to a first single-bit stream. A first filter positioned on the second side may be configured to receive the first single-bit stream across the first isolator and to generate a first reconstructed multi-bit digital signal using the first single-bit stream.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 14, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Ryan Pinto, Jonathan Ephraim David Hurwitz, Lawrence Getzin
  • Publication number: 20210275045
    Abstract: One or more electromagnetic radiation sources, such as a light emitting diode, may emit electromagnetic waves into a volume of space. When an object enters the volume of space, the electromagnetic waves may reflect off the object and strike one or more position sensitive detectors after passing through an imaging optical system such as glass, plastic lens, or a pinhole located at known distances from the sources. Mixed signal electronics may process detected signals at the position sensitive detectors to calculate position information as well as total reflected light intensity, which may be used in medical and other applications. A transparent barrier may separate the sources and detectors from the objects entering the volume of space and reflecting emitted waves. Methods and devices are provided.
    Type: Application
    Filed: February 16, 2021
    Publication date: September 9, 2021
    Applicant: Analog Devices, Inc.
    Inventor: Shrenik DELIWALA
  • Publication number: 20210281676
    Abstract: Disclosed herein are proximity detection sensor arrangements, as well as related methods and devices. In some embodiments, a sensor arrangement in an electronic device may include a first circuit layer including a proximity pad and a first reference pad, and a second circuit layer including a second reference pad and a temperature pad. The first circuit layer may be between the second circuit layer and a user-facing surface of the electronic device, the first reference pad may be electrically coupled to the second reference pad, and the first reference pad may be between the temperature pad and the user-facing surface.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 9, 2021
    Applicant: Analog Devices International Unlimited Company
    Inventors: Xiangzhi WU, Hsien-Chieh LIU
  • Publication number: 20210278847
    Abstract: Navigation systems and methods for autonomous vehicles are provided. The navigation system may include multiple navigation subsystems, including one having an inertial measurement unit (IMU). That unit may serve as the primary unit for navigation purposes, with other navigation subsystems being treated as secondary. The other navigation subsystems may include global positioning system (GPS) sensors, and perception sensors. In some embodiments, the navigation system may include a first filter for the IMU sensor and separate filters for the other navigation subsystems.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 9, 2021
    Applicant: Analog Devices, Inc.
    Inventors: Igor P. Prikhodko, Joseph Bergeron, Alan Christopher O'Connor
  • Patent number: 11112436
    Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: David J. Clarke, Stephen Denis Heffernan, Nijun Wei, Alan J. O'Donnell, Patrick Martin McGuinness, Shaun Bradley, Edward John Coyne, David Aherne, David M. Boland
  • Patent number: 11112269
    Abstract: Techniques for self-testing of microelectromechanical systems (MEMS) inertial sensors are described. Some techniques involve testing inertial sensor characteristics such as an accelerometer's sensitivity to acceleration and a gyroscope's sensitivity to angular motion. The tests may be performed by providing a test signal, which simulates a stimulus such as an acceleration or angular rate, to a MEMS inertial sensor and examining the sensor's output. The efficacy of such self-tests may be impaired by spurious signals, which may be present in the sensor's environment and may influence the sensor's output. Accordingly, the self-testing techniques described herein involve detecting the presence of any such spurious signals and discarding self-test results when their presence is detected. In some embodiments, the presence of spurious signals may be detected using a signal obtained by mixing the response of the MEMS inertial sensor with a reference signal substantially in quadrature with the test signal.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 7, 2021
    Assignee: Analog Devices, Inc.
    Inventor: William A. Clark
  • Patent number: 11105843
    Abstract: A stabilization technique is disclosed that suppresses or inhibits glitching behavior on automated test equipment (ATE) during mode transitions. Adjustable stabilizing circuitry can be coupled to at least one of a force voltage circuit or a force current circuit is forcing voltage or current to a device under test (DUT). The adjustable stabilizing circuitry can be adjustably configurable in response to whether at least one of a current clamp or a voltage clamp is in an active clamping mode. In this manner, unwanted glitching behavior associated with mode changes can be reduced or suppressed.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Amit Kumar Singh, Christopher C. McQuilkin