Abstract: The techniques of this disclosure can cancel or reduce the kT/C noise directly before the gain stage. The effect of the kT/C noise can be greatly reduced, allowing both lower noise conversion and smaller sampling capacitors, which can reduce the die area and reduce the power consumption of the ADC.

Abstract: An example current mirror arrangement includes a current mirror circuit having an input transistor and an output transistor, where the base/gate terminal of the input transistor is coupled to its collector/drain terminal via a transistor matrix that includes a plurality of transistors. Transistors of the transistor matrix, together with the input transistor, form two parallel feedback loops, such that the input transistor is part of both loops. The first loop is a fast, low-gain loop, while the second loop is a slow, high-gain loop. At lower input frequencies, the high-gain loop may properly bias and accurately generate voltage at the base/gate terminal of the input transistor, while at higher input frequencies the fast loop may significantly extend the linear operating frequency band. Consequently, a current mirror arrangement with improvements in terms of linearity and signal bandwidth may be realized.

Abstract: Herein disclosed in some embodiments is a fault detector for power amplifiers of a communication system. The fault detector can detect a portion of the power amplifiers that are in fault condition and can prevent or limit current flow to the power amplifiers in fault condition while allowing the rest of the power amplifiers to operate normally. The fault detector can further indicate which power amplifiers are in fault condition and/or the cause for the power amplifiers to be in fault condition. Based on the indication, a controller can direct communications away from the power amplifiers in fault condition and/or perform operations to correct the fault condition.

Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Abstract: Microelectromechanical system (MEMS) accelerometers are described. The MEMS accelerometers may include multiple proof mass portions collectively forming one proof mass. The entirety of the proof mass may contribute to detection of in-plane acceleration and out-of-plane acceleration. The MEMS accelerometers may detect in-plane and out-of-plane acceleration in a differential fashion. In response to out-of-plane accelerations, some MEMS accelerometers may experience butterfly modes, where one proof mass portion rotates counterclockwise relative to an axis while at the same time another proof mass portion rotates clockwise relative to the same axis. In response to in-plane acceleration, the proof mass portions may experience common translational modes, where the proof mass portions move in the plane along the same direction.

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

Abstract: Techniques for wirelessly charging smart textiles, such as smart garments, are provided. Aspects of the present application provide a smart garment device with an array of integrated coils and rectifiers that enable wireless charging of the device from a drawer or other enclosure that produces a roughly uniform AC magnetic field. The smart garment can draw power from the magnetic field once placed within the enclosure, regardless of how the garment is placed in the enclosure. The method can be applied to garments of any shape, and multiple garments can be charged simultaneously by placing the multiple garments into the same magnetic field.

Abstract: Coupled line structures for wideband applications are provided herein. In certain embodiments, a coupled line structure includes one transmission line that is segmented in a metal layer and another that is substantially continuous in the metal layer, thereby allowing tighter spacing and higher coupling between the transmission lines relative to what is achievable if both transmission lines were continuous. The high coupling in turn aids in achieving wide bandwidth.

Abstract: The present disclosure relates to a PUF apparatus and method for generating a persistent, random number. The generated number is random in that each particular instance of PUF apparatus should generate a randomly different number to all other instances of PUF apparatus, and is persistent in that each particular instance of the PUF apparatus should repeatedly generate the same number, within acceptable error correction tolerances. The persistent, random number is determined by selecting one or more PUF cells, each comprising a matched pair of transistors that are of identical design, and comparing an on-state characteristic of the pair (e.g., turn-on threshold voltage or gate-source voltage). The difference in on-state characteristic of each selected pair of transistors is caused by random manufacturing differences between the transistors. This causes the randomness between each different instance of PUF apparatus, and should be relatively stable over time to provide persistence of the generated number.

Abstract: Provided herein are semiconductor dies including multiple controllers for operating over an extended temperature range. In certain embodiments, a semiconductor die includes multiple circuit modules, a temperature sensor that generates a detected temperature signal, an interface that communicates with an external host, a primary controller coupled to the interface and operable to control the circuit modules, and a secondary controller coupled to the interface. In response to the detected temperature signal indicating that the temperature of the semiconductor die exceeds a threshold temperature, the primary controller enables the secondary controller, which in turn disables the primary controller and at least a portion of the plurality of circuit modules to reduce heat dissipation.

Abstract: Polyphase filters (PPFs) can be used to generate quadrature or other phase-shifted representations of an input signal provided to the PPF. In one approach, a “passive” polyphase filter can include a combination of resistive and capacitive elements. Such a topology can be referred to as an RC-PPF topology. Another passive circuit topology can be used to provide a PPF, by replacing the resistive elements with inductive elements, and by replacing the capacitive elements with resistive elements. A filter circuit can include cascaded RC-PPF and LR-PPF sections, such as in an alternating manner (e.g., an “RC-LR” topology). In this approach, a total insertion loss of cascaded LR-PPF and RC-PPF sections can be reduced as compared to using LR-PPF or RC-PPF sections, alone.

Abstract: The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy.

Abstract: Embodiments of the present disclosure relate to cellular technology applications of beamforming performed in the digital domain. In one aspect, an RF system for performing digital beamforming on a per-carrier basis is disclosed, where different phase and/or amplitude adjustments are applied to signals of different frequency ranges (i.e., to different carrier signals). In another aspect, an RF system for performing digital beamforming on a per-antenna basis is disclosed, where different phase and/or amplitude adjustments are applied to signals transmitted from or received by different antennas. In some embodiments, an RF system may be configured to implement both digital beamforming on a per-carrier basis and digital beamforming on a per-antenna basis. The RF systems disclosed herein allow implementing programmable beamforming in the digital domain in a manner that is significantly less complex than conventional implementations.

Abstract: A device to reduce distortion in an amplifier includes an input transistor configured to generate a voltage based on an input signal. The device further includes a diode connected transistor that is configured to sink the current. The diode connected transistor includes an output terminal, and a control terminal, where the output terminal is coupled to a control terminal. The device further includes a current source circuit that coupled to the control terminal. The device additionally includes an impedance element that coupled to the output terminal at a first node and to the control terminal and the current source circuit at a second node.

Abstract: Depth imagers can implement time-of-flight operations to measure depth or distance of objects. A depth imager can emit light onto a scene and sense light reflected back from the objects in the scene using an array of sensors. Timing of the reflected light hitting the array of sensors gives information about the depth or distance of objects in the scene. In some cases, corrupting light that is outside of a field of view of a pixel in the array of sensors can hit the pixel due to internal scattering or internal reflections occurring in the depth imager. The corrupting light can corrupt the depth or distance measurement. To address this problem, an improved depth imager can isolate and measure the corrupting light due to internal scattering or internal reflections occurring in the depth imager, and systematically remove the measured corrupting light from the depth or distance measurement.

Abstract: Disclosed herein are transimpedance circuits, as well as related methods and devices. In some embodiments, a transimpedance circuit may include a current source bias terminal, a current source output terminal, and a transimpedance amplifier coupled to the current source output terminal, wherein voltage signals at the current source bias terminal are correlated with voltage signals at the current source output terminal. In some embodiments, the current source may be a photodiode.

Abstract: Disclosed herein are transconductance circuits, as well as related methods and devices. In some embodiments, a transconductance circuit may include an amplifier having a first input coupled to a voltage input of the transconductance circuit, and a switch coupled between an output of the amplifier and a second input of the amplifier.

Abstract: Micro-scale devices, such as transformers and capacitors, having a floating conductive layer are disclosed. A floating conductive layer may be disposed in an insulator layer and can reduce a maximum electric field between a first planar conductor and a second planar conductor of a micro-scale passive device. Reduction of a maximum electric field between a first planar conductor and a second planar conductor can reduce undesirable effects on electrical components.

Abstract: An amplifier circuit comprises a differential input stage and a differential output stage. The differential input stage includes a first differential input transistor pair coupled to a differential input of the amplifier circuit, and a second differential input transistor pair coupled to the differential input and the differential output stage; a degeneration impedance coupled between first transistors of the first and second differential input transistor pairs and second transistors of the first and second differential input transistor pairs; and a feedback circuit coupled to the first and second differential input transistor pairs and the degeneration impedance, wherein output current is provided from the differential input stage to the differential output stage by the feedback circuit and transition current is provided to the output stage by the second differential input transistor pair.

Abstract: Bias arrangements for amplifiers are disclosed. An example bias arrangement for an amplifier includes a bias circuit, configured to produce a bias signal for the amplifier; a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal produced by the bias circuit to produce a modified bias signal to be provided to the amplifier; and a coupling circuit, configured to couple the bias circuit and the linearization circuit. Providing separate bias and linearization circuits coupled to one another by a coupling circuit allows separating a linearization operation from a biasing loop to overcome some drawbacks of prior art bias arrangements that utilize a single biasing loop.