Abstract: Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region, a second p-well region, and an n-well region positioned between the first and second p-wells regions. The bidirectional clamp further includes two or more oxide regions over the n-well region, and one or more n-type active (N+) dummy blocking current regions are positioned between the oxide regions. The one or more N+ dummy leakage current blocking regions interrupt an electrical path from the first p-type well region to the second p-type well region along interfaces between the n-well region and the oxide regions. Thus, even when charge accumulates at the interfaces due to extended high voltage, e.g., >60V, and/or high temperature operation (e.g., >125° C.), the N+ dummy leakage current blocking regions inhibit charge trapping-induced leakage current.

Abstract: An electric energy scavenger device has a housing forming an internal chamber with an internal wall, and a movable element contained within the internal chamber. The movable element is freely movable and unconnected to any other movable element within the internal chamber. Within the internal chamber, the device also has a plurality of piezoelectric charge conversion elements positioned along the internal wall. The plurality of piezoelectric charge conversion elements are positioned side-by-side to contact the movable element when the movable element moves within the internal chamber. In addition, the movable element is configured to simultaneously contact at least two of the plurality of side-by-side piezoelectric charge conversion elements. During use, the movable element is freely movable within the internal chamber in response to movement of the entire housing.

Abstract: Speakers do not always operate linearly. Linearity of the speaker can affect the quality of the sound produced by the speaker, i.e., causing distortions in the sound, if the nonlinearites are not accounted for. To determine nonlinearities of the speaker, the speaker is often modeled and measurements are made to estimate the characteristics of the speaker based on the model. By using an angle sensor and a light source, a speaker manager can make a direct measurement of excursion or displacement of the speaker. Moreover, when the angle sensor, the light source, and the light beam are configured appropriately with respect to the moving cone of the speaker, the measurement can be substantially linear with respect to the amount of excursion or displacement. Such measurements are far simpler to use and in some cases more accurate than measurements made by other types of systems.

Abstract: An authentication system and device including physical unclonable function (PUF) and threshold cryptography comprising: a PUF device having a PUF input and a PUF output and constructed to generate, in response to the input of a challenge, an output value characteristic to the PUF and the challenge; and a processor having a processor input that is connected to the PUF output, and having a processor output connected to the PUF input, the processor configured to: control the issuance of challenges to the PUF input via the processor output, receive output from the PUF output, combine multiple received PUF output values each corresponding to a share of a private key or secret, and perform threshold cryptographic operations. The system and device may be configured so that shares are refreshable, and may be configured to perform staggered share refreshing.

Abstract: In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

Abstract: A digital pre-distortion system can inversely model a power amplifier of a system to linearize the transmitter. A complex baseband model for digital pre-distortion based on a narrowband signal assumption is unworkable for an ultra wide band Cable television application. Predistortion can use a true wide band model including real-valued basis terms, obtained from a real-valued signal. When raised to a power, both even and odd harmonics or both odd or even other non-linear terms are represented and negative frequency fold-over can be accounted for. A Hilbert transform can be applied. Compressed sensing can be used to reduce the number of basis terms in the true real wide band model to generate a sparse model. Sparse equalization can be added to improve the stability of the digital pre-distortion system.

Abstract: Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: Methods, apparatuses, and systems can be provided to implement active feedback to electrically sense or monitor the illumination and shutter pulses and adjust them actively to maintain the desired phase relationship/difference between the pulses. By maintaining the desired phase difference, the distance calculation can be made more accurate, even when conditions of the time-of-flight camera varies (e.g., temperature, aging, etc.). Advantageously, active compensation can correct for errors ‘on-the-fly’, eliminating detailed characterization and manual adjustment during operation.

Abstract: An impedance matching circuit is provided for use with a piezotransducer that includes a parasitic capacitor comprising: an inductor coupled in parallel with the parasitic capacitor; a peak and valley detection circuit configured to detect output voltage waveform peaks and valleys; a first switch circuit configured to bias flip the output voltage waveform at a selectable first time relative to a detected peak and at a selectable first time relative to a detected valley; a second switch circuit configured to couple the inductor to the energy storage circuit at a selectable second time following each output voltage bias flip; an energy monitoring circuit to provide an indication of energy flow from the inductor to the energy storage circuit following each output voltage bias flip; and a maximum power point tracking (MPPT) circuit configured to select the first time and the second time based at least in part upon the indicated energy flow.

Abstract: A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

Abstract: An electrical circuit includes a sensor configured to generate a current signal comprising a first portion comprising a contribution from a target source and/or a second portion comprising a contribution from sources other than the target source, a trans-impedance amplifier that amplifies the current signal and generate a low noise signal, and a high pass filter that converts the low noise signal into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive and negative amplitudes. The circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The circuit further includes at least one analog-to-digital converter that receives the integrated values.

Abstract: A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.

Abstract: A microelectromechanical system (MEMS) accelerometer is described. The MEMS accelerometer is arranged to limit distortions in the detection signal caused by displacement of the anchor(s) connecting the MEMS accelerometer to the underlying substrate. The MEMS accelerometer may include masses arranged to move in opposite directions in response to an acceleration of the MEMS accelerometer, and to move in the same direction in response to displacement of the anchor(s). The masses may, for example, be hingedly coupled to a beam in a teeter-totter configuration. Motion of the masses in response to acceleration and anchor displacement may be detected using capacitive sensors.

Abstract: Micro-fabricated coils are described. In some situations, the micro-fabricated coils include interleaved coils. In some situations, pairs of interleaved coils are stacked with respect to each other, separated by an insulating material. In some situations, the interleaved coils have an S-shape. The interleaved coils may be employed in a galvanic isolator.

Abstract: An integrated circuit has a substrate, a super-capacitor supported by the substrate, and a battery supported by the substrate. The super-capacitor includes a super-capacitor electrode and a shared electrode, and the battery has a battery electrode and the prior noted shared electrode. The super-capacitor and battery form at least a part of a monolithic integrated circuit.

Abstract: In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures.

Abstract: A receiver apparatus models and corrects the frequency-dependent and the frequency-independent mismatches between I and Q paths jointly by polynomial estimations. The receiver apparatus may sample digitized I and Q path signals. The sampled data point may be modeled in equations with real and imaginary components. The sampled discrete time-domain data may be converted to frequency-domain data. Multiple statistics values based on the frequency-domain data may be computed. Coefficients for the polynomial equations may be estimated based on the computed statistic values. The channel mismatches may be estimated from the polynomial equations and used to compensate the mismatch either on the I path or the Q path.

Abstract: Embodiments of the present disclosure provide mechanisms that enable designing an FIR filter that would have a guaranteed globally optimal magnitude response in terms of the minimax optimality criterion given a desired weight on the error in the stopband versus the passband. Design of such a filter is based on a theorem (“characterization theorem”) that provides an approach for characterizing the global minimax optimality of a given FIR filter h[n], n=0, 1, . . . , N, where optimality is evaluated with respect to a magnitude response of this filter, |H(ej?)|, as compared to the desired filter response, D(?), which is unity in the passband and zero in the stopband. The characterization theorem enables characterizing optimality for both real-valued and complex-valued filter coefficients, and does not require any symmetry in the coefficients, thus being applicable to all non-linear phase FIR filters.

Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.