Abstract: A wide range differential current switching circuit can operate across a wide range of input currents and across a broad range of frequencies. A first differential current source can include a first transistor and a second transistor. The first transistor receives a switching signal and provides an output current and at output node. The second transistor receives an inverted switching signal, the first transistor and the second transistor coupled to each other at a tail node. A current source provides an input current to the tail node. A third transistor can provide a boost current to the tail node while the first transistor is off.

Abstract: A method of fabricating a super-capacitor provides a substrate, and then adds an electrode and electrolyte template film, having a well for receiving the electrode, to the substrate. The method also adds a second electrolyte to the electrode and electrolyte template.

Abstract: A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods.

Abstract: Residue generation systems for use in continuous-time and hybrid ADCs are described. An exemplary system includes a filter, e.g. a FIR filter, for generating a filtered analog output based on an analog input, a quantizer for generating a digital input to a feedforward DAC based on the filtered analog output generated by the filter, a feedforward DAC for generating a feedforward path analog output based on the digital input generated by the quantizer, and a subtractor for generating a residue signal based on the feedforward path analog output. Providing a filter that filters the analog input before it is quantized advantageously allows blockers to be attenuated before they are sampled and aliased by the quantizer. At least some of the residue generation systems described herein may be implemented with relatively small design and power dissipation overheads.

Abstract: Disclosed herein are systems and techniques for adaptive use of multiple power supplies in a communication system. For example, in some embodiments, a slave device may include: an upstream transceiver to couple to an upstream link of a bus of a communication system; and circuitry to couple to the upstream link of the bus and to a local power supply, wherein the circuitry is to switch from providing the local power supply to power the slave device to providing bus power supplied by the upstream link of the bus to power the slave device.

Abstract: An microelectromechanical switch uses electrostatic attraction to draw a beam toward a contact and electromagnetic repulsion to disengage and repel the beam from the contact. The electrostatic attraction is generated by a gate electrode. The electromagnetic repulsion is generated between the beam and a magnetic coil positioned on the same side of the beam as the contact. The magnetic coil produces a magnetic field, which induces a current in the beam that repels the magnetic coil. The gate electrode and the magnetic coil may be co-planar or in different planes. A circuit may also operate a coil-shaped structure act as the gate electrode and the magnetic coil, depending on the configuration.

Abstract: A delta-sigma modulator circuit comprising: an integrator circuit configured to produce an integrator output signal that represents an integration of an analog input signal, a comparator output signal and a periodic signal; a comparator circuit configured to produce the comparator output signal in response to a comparison of the integrator output signal with a first reference signal; and a periodic signal generation circuit configured to produce the periodic signal.

Abstract: Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, the interface circuit can provide a selectable impedance.

Abstract: A protection device is provided that is placed in series connection between an input or signal node and a node to be protected. If the node to be protected is a relatively high impedance node, such as the gate of a MOSFET, then the protection device need not carry much current. This enables it to be built to be very fast. This enables it to respond rapidly to an overvoltage event so as to protect the circuit connected to the node to be protected. The protection device may be used in conjunction with other protection cells that offer greater current carrying capability and controllable trigger voltages, but which are intrinsically slower acting.

Abstract: A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.

Abstract: A method of and apparatus for protecting a MEMS switch is provided. The method and apparatus improve the integrity of MEMS switches by reducing their vulnerability to current flow through them during switching of the MEMS switch between on and off or vice versa. The protection circuit provides for a parallel path, known as a shunt, around the MEMS component. However, components within the shunt circuit can themselves be removed from the shunt when they are not required. This improves the electrical performance of the shunt when the switch is supposed to be in an off state.

Abstract: For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.

Abstract: Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel. For this purpose, the clock output signals from the various independent blocks are first mutually aligned in proper order using a lower speed clock, and subsequently offset from one another such that sampling instances of the various sampler blocks are interleaved. Digitized data words corresponding to common input data and outputted by the various sampler blocks are compared after alignment of the clock output signals to correct additional timing misalignment between the multiple sampler blocks. The digitized data words need only be aligned once or at most infrequently after the clock output signals are aligned, since the additional timing misalignment is caused mainly path delays that are substantially invariant over time.

Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

Abstract: Apparatus and techniques described herein can include a load circuit comprising a direct current (DC) input terminal, and a source circuit comprising a direct current (DC) output terminal coupled to the DC input terminal of the load circuit. The source circuit can include a source control circuit configured to provide a current-limited DC output voltage and monitor the current-limited DC output voltage to detect an authentication signal provided at the DC output terminal by the load circuit, the load circuit configured to modulate the voltage at the DC output terminal using a pull-down circuit. The load circuit can be configured to compare the supply voltage at the DC input terminal to a reference voltage and, in response, energize other portions of the load circuit when the input current provided the DC input terminal is sufficient as indicated at least in part by the comparison.

Abstract: Various embodiments mitigate the risk of frequency-lock in systems having multiple resonators by dynamically changing the frequency at which at least one of the resonators is driven. More particularly, the drive frequency of at least one of the resonators is changed often enough that the multiple resonators do not have time to achieve frequency lock. Changes in the oscillation of the resonators may be analyzed to determine, for example, acceleration of such systems. Some embodiments implement self-test by assessing expected performance of a system with toggling drive frequencies. More particularly, some embodiments implement self-test by artificially inducing displacement of a movable member of a system.

Abstract: A MEMS product includes a stress-isolated MEMS platform surrounded by a stress-relief gap and suspended from a substrate. The stress-relief gap provides a barrier against the transmission of mechanical stress from the substrate to the platform.

Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.

Abstract: Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

Abstract: A capacitive gain amplifier circuit amplifies an input signal by a pair of differential amplifier circuits couples in series. The first differential amplifier circuit is reset during an autozero phase while disconnected from the second differential amplifier circuit, and the first and second differential amplifier circuits are connected together in series during a chop phase. A set of feedback capacitors is selectively switched in between respective outputs of the second differential amplifier circuit and respective inputs of the first differential amplifier circuit during the chop phase.