Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

Abstract: A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/ subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.

Abstract: Methods and apparatus for anchoring resonators, such as microelectromechanical systems (MEMS) resonators. A resonator may include a substrate, a mechanical resonating structure, and at least one anchor. The mechanical resonating structure may be configured to resonate in a resonance mode of vibration at a frequency. The anchor may couple the mechanical resonating structure to the substrate. The anchor may be configured to exhibit an acoustic bandgap at the frequency of the resonance mode of vibration of the mechanical resonating structure. The anchor may be oriented in a direction substantially parallel to a direction of propagation of the resonance mode of vibration of the mechanical resonating structure.

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.

Abstract: Many systems implement calibration schemes to measure and correct for the non-idealities. Such systems can be complex, which makes them impractical to implement since the cost can potentially outweigh the benefits of the calibration scheme. To implement efficient and effective calibration, non-idealities or errors of a system are detected, in foreground or in background, in a piecewise fashion based on, e.g., correlations of an output signal with an uncorrelated random signal, where the correlation results are processed separately for different open intervals of an error signal. Second order and third order correction terms can be easily determined based on three open intervals. In various embodiments, the calibration scheme can detect and correct for linear errors, (linear and non-linear) memory/frequency dependent errors, static nonlinearity errors, Hammerstein-style non-linearity errors, and Wiener-style non-linearity errors (cross-terms).

Abstract: Circuits are used to sense and compensate or mitigate the imbalance errors, hence restoring the intended benefits of differential processing. In particular, the impedance mismatch between the positive and negative branches of a balanced system is sensed by digitizing an error voltage developed by injecting suitable common mode stimuli. The mismatch is then trimmed out by introducing and properly setting up a digitally controlled impedance that counters the original impedance mismatch and hence rebalances the signal path on-situ and prior to exercising the signal processing chain.

Abstract: In an example, there is disclosed a computing apparatus, having: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, wherein the second ordinal QoS profile is higher in order than the first ordinal QoS profile; a slave; a multiplexed interconnect to communicatively couple the first master and second master to the slave with a priority according to the ordinal QoS profiles; and one or more logic elements, including at least one hardware logic element, providing a QoS engine to: determine that the first master has initiated a slave operation via the interconnect; determine that completing the slave operation according to a QoS criterion provided by the second master requires elevated QoS; and promote the first master to a third ordinal QoS profile having an order higher than the second ordinal QoS profile.

Abstract: Disclosed herein are systems and technique for distributed audio coordination over a two-wire communication bus. For example, in some embodiments, a first slave device may include circuitry to receive, over a two-wire bus a synchronization control frame, audio data, and a dynamics processor (DP) parameter for a second audio device coupled to a second slave device. The first slave device may include circuitry to derive timing information from the synchronization control frame, and circuitry to provide the audio data and a DP parameter (based on the DP parameter for the second audio device) to a first audio device coupled to the first slave device.

Abstract: Digital to analog converters (DAC) are used to convert digital signals to analog values. The digital system providing data to the analog converter may be highly tasked. A DAC is provided with some in built logic to assist in reducing the load on the devices driving the DAC. The DAC may include a library of functions that it can apply to the input words to modify transitions in the analog output words. The DAC may further include a health checking system for monitoring the digital words being supplied to the DAC and raising a concern, and taking action if required, if the sequence of words is unlikely to be correct or beyond the target operating range.

Abstract: Heart rate monitors are plagued by noisy photoplethysmography (PPG) data, which makes it difficult for the monitors to output a consistently accurate heart rate reading. Noise is often caused by motion. Using known methods for processing accelerometer readings that measure movement to filter out some of this noise may help, but not always. The present disclosure describes an improved front-end technique (time-domain interference removal) based on using adaptive linear prediction on accelerometer data to generate filters for filtering the PPG signal prior to tracking the frequency of the heartbeat (heart rate). The present disclosure also describes an improved back-end technique based on steering the frequency of a resonant filter in order to track the heartbeat. Implementing one or both of these techniques leads to more accurate heart rate measurements.

Abstract: Many systems implement calibration schemes to measure and correct for the non-idealities. Such systems can be complex, which makes them impractical to implement since the cost can potentially outweigh the benefits of the calibration scheme. To implement efficient and effective calibration, non-idealities or errors of a system are detected, in foreground or in background, in a piecewise fashion based on, e.g., correlations of an output signal with an uncorrelated random signal, where the correlation results are processed separately for different open intervals of an error signal. Second order and third order correction terms can be easily determined based on three open intervals. In various embodiments, the calibration scheme can detect and correct for linear errors, (linear and non-linear) memory/frequency dependent errors, static nonlinearity errors, Hammerstein-style non-linearity errors, and Wiener-style non-linearity errors (cross-terms).

Abstract: A method for generating a Fast Fourier Transform (FFT) is disclosed. The method includes providing an input signal to two or more fixed-point FFT algorithms that apply different scaling to reduce growth of their output, resulting in each of the FFT algorithms yielding an array of FFT output values characterized by a different gain. The method further includes determining, on a per-FFT output value basis, whether an output value of an FFT algorithm with a relatively high gain was clipped due to saturation. If not, then the output value of that FFT algorithm is included in the final FFT. Otherwise, an output value of an FFT algorithm with a lower gain is included in the final FFT. Reconstructing the final FFT by such combination of values from different FFTs allows benefiting from the advantages of both higher- and lower-gain FFTs while avoiding or minimizing their disadvantages.

Abstract: Disclosed herein are systems and techniques for peripheral device diagnostics and control over a two-wire communication bus. For example, in some embodiments, a slave device may include circuitry to receive a synchronization control frame from an upstream device, receive audio data from the upstream device subsequent to receipt of the synchronization control frame, provide a synchronization response frame toward the upstream device, and provide first data representative of an operational characteristic of an audio device coupled to the slave device subsequent to provision of the synchronization response frame; circuitry to derive timing information from the synchronization control frame; and circuitry to provide the audio data to the audio device, and receive, from a sensor coupled to the slave device, second data representative of the operational characteristic of the audio device.

Abstract: A DC-DC converter for supplying a gradually increasing voltage via a soft start circuit from a first powered domain to a second unpowered domain. The powered domain may be connected to a primary winding of a first transformer, and the unpowered domain may be connected to the secondary winding of the first transformer. The unpowered domain may respond to an applied voltage from the soft start circuit by supplying a feedback signal to the powered domain via a feedback circuit. The feedback signal indicates the power supplied from the secondary winding of the first transformer to the unpowered domain is satisfactory.

Abstract: An authentication system and device including physical unclonable function (PUF) and threshold cryptography comprising: a PUF device having a PUF input and a PUF output and constructed to generate, in response to the input of a challenge, an output value characteristic to the PUF and the challenge; and a processor having a processor input that is connected to the PUF output, and having a processor output connected to the PUF input, the processor configured to: control the issuance of challenges to the PUF input via the processor output, receive output from the PUF output, combine multiple received PUF output values each corresponding to a share of a private key or secret, and perform threshold cryptographic operations. The system and device may be configured so that shares are refreshable, and may be configured to perform staggered share refreshing.

Abstract: Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel. For this purpose, the clock output signals from the various independent blocks are first mutually aligned in proper order using a lower speed clock, and subsequently offset from one another such that sampling instances of the various sampler blocks are interleaved. Digitized data words corresponding to common input data and outputted by the various sampler blocks are compared after alignment of the clock output signals to correct additional timing misalignment between the multiple sampler blocks. The digitized data words need only be aligned once or at most infrequently after the clock output signals are aligned, since the additional timing misalignment is caused mainly path delays that are substantially invariant over time.

Abstract: A microelectromechanical systems (MEMS) sensor device with a compound folded tether is disclosed. The compound folded tether connects a movable proof mass to a substrate, and includes folds composed of multiple short segments aligned with each other to form a longer composite segment having multiple breaks along its length. The use of multiple short segments to create a longer composite segment of the folded tether provides the tether with increased stiffness without altering the fundamental resonance frequency of the tether. The increased stiffness can beneficially lower the occurrence of stiction. Moreover, such a tether configuration provides larger separation between the tether's fundamental resonance frequency and higher order resonant mode frequencies, meaning that the higher order modes may be suppressed in typical operation of the MEMS sensor device.

Abstract: The present invention relates to current measurement apparatus 100. The current measurement apparatus 100 comprises a measurement arrangement 110, 114 which is configured to be disposed in relation to a load 108 which draws a current signal, the measurement arrangement being operative when so disposed to measure the load drawn current signal. The current measurement apparatus 100 also comprises a signal source 112 which is operative to apply a reference input signal to the measurement arrangement 110, 114 whereby an output signal from the measurement arrangement comprises a load output signal corresponding to the load drawn current signal and a reference output signal corresponding to the reference input signal.

Abstract: Embodiments of the present invention may provide a method of measuring an unknown capacitance of a device. The method may comprise the steps of driving a test signal to a circuit system that includes a current divider formed by the device with unknown capacitance and a reference capacitor; mirroring a current developed in the reference capacitor to a second circuit system that includes a measurement impedance; measuring a voltage within the second circuit system; and deriving a capacitance of the unknown capacitance based on the measured voltage with reference to a capacitance of the reference capacitor and the measurement impedance.

Abstract: A multiple output, multiple impedance string digital-to-analog converter (DAC) circuit can provide a first output having a first resolution in response to a first digital input signal and a second output having a second resolution in response to a second digital input signal. A main impedance string and a secondary impedance string can be coupled using switching networks to provide a first DAC output. By coupling additional switches to the main impedance string and by sharing the main impedance string, a second DAC output can be realized.