Abstract: Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

Abstract: A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.

Abstract: Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a substrate, a wall attached to the substrate, a first adhesive layer disposed between a bottom surface of the wall and a top surface of the substrate, and a second adhesive layer disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer different from the first adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground.

Abstract: A method compensates for a sensitivity of an inertial sensor having a resonator and an accelerometer. The method includes adding a test signal to a quadrature tuning voltage applied to the resonator of the inertial sensor. The method also includes receiving a quadrature error signal from the accelerometer of the inertial sensor. The method also includes detecting a phase difference between the quadrature error signal and the test signal. The method also includes determining a bandwidth of the accelerometer based on the detected phase difference, the bandwidth indicating the sensitivity of the accelerometer.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on.

Abstract: A delta-Vbe based bandgap reference voltage circuit generates a temperature stable reference voltage. First and second paths of the circuit each include a respective transistor coupled in series with a resistance. The collector current density of the transistor in first path is lower than the collector current density of transistor in the other path. A control path is used to generate a 2Vbe voltage that is coupled to the base nodes of the resistors in each path. A resistance that is coupled between a common node of a first end of the two paths and a circuit ground node. The circuit current is controlled by this resistance and a voltage drop of 2?Vbe is across the resistance. The output reference voltage of the circuit is 2(Vbe+?Vbe) when stack resistors in each path are used.

Abstract: A power converter can include an electrical isolation circuit between input and output nodes. An input signal monitor node can be provided, such as on a converter output side of the isolation circuit. In an example, a peak detection circuit can be coupled to the input signal monitor node. The output node of the power converter can be configured to supply an output power signal that is a function of an input signal at the input node. The power converter can include multiple, independently-switchable switches at one or more of the input and output sides of the isolation circuit. In an example, the power converter with the input signal monitor node can be configured as a bias supply to provide power, at the output node, to a controller circuit for a main stage power converter circuit.

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract: Activity monitors and smart watches utilizing optical measurements are becoming widely popular, and users expect to get an increasingly accurate estimate of their heart rate (HR) from these devices. These devices are equipped with a light source and an optical sensor which enable estimation of HR using a technique called photoplethysmography (PPG). One of the main challenges of HR estimation using PPG is the coupling of motion into the optical PPG signal when the user is moving randomly or exercising. The present disclosure describes a computationally feasible and fast HR estimation algorithm to be executed at instances of little or no motion. Resulting HR readings may be useful on their own, or be provided to systems that monitor HR continuously to prevent the problem of such systems being locked on an incorrect HR for long periods of time. Implementing techniques described herein leads to more accurate HR measurements.

Abstract: A transformer based isolated bi-directional DC-DC power converter may have signals for controlling power transfer in first and second directions are derived from the same side of the transformer. The converter may include a transformer, a first switching circuit, a second switching circuit, and a controller. In a first mode, the controller controls the first and second switching circuits, and power is transferred from a first side to a second side. In a second mode, the controller controls the first and second switching circuits, and power is transferred from the second side to the first side.

Abstract: An analog to digital converter (ADC) system includes two signal paths in parallel with each other, where the signal paths include separate ADC circuits to separately operate on a same input signal and output separate digital signals. A difference signal is calculated as a difference of the digital signals output from the two signal paths to determine an error present in one or both of the signal paths. The error may be modulated in one or both of the signal paths and demodulated from the difference signal according to a same digital modulation pattern to compute an error compensation signal to compensate for at least one of the modulated error and a secondary error resulting from the modulation of the error.

Abstract: A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.

Abstract: A wideband RF tuner with blocker signal detector for detection of blocking signals and for fast recovery from noise limited region.

Abstract: A capacitive microelectromechanical systems (MEMS) sensor is provided, having conductive coatings on opposing surfaces of capacitive structures. The capacitive structures may be formed of silicon, and the conductive coating is formed of tungsten in some embodiments. The structure is formed in some embodiments by first releasing the silicon structures and then selectively coating them in the conductive material. In some embodiments, the coating may result in encapsulating the capacitive structures.

Abstract: A circuit structure that includes a plurality of stacked conductor layers separated from each other by respective dielectric layers. The conductor layers may include a first set of conductor layers made of a first type conductor material and a second set of conductor layers made of a second type conductor material different from the first. A pair of conductor posts may traverse the stacked conductor layers. A first post may be electrically connected to the first set of conductor layers and electrically insulated from the second set of conductor layers. A second post electrically connected to the second set of conductor layers and electrically insulated from the first set of conductor layers.

Abstract: Disclosed herein are microphone arrays for directional reception, along with related system, devices, and techniques. For example, a four-microphone array for directional signal reception may include first, second, and third microphones arranged such that projections of the first, second, and third microphones in a plane provide corners of a triangle in the plane. In some embodiments, a fourth microphone may be arranged such that a projection of the fourth microphone in the plane is disposed in an interior of the triangle. In other embodiments, the fourth microphone may be arranged such that the projection of the fourth microphone in the plane is disposed outside the interior of the triangle, and a distance between the first microphone and the second microphone is different from a distance between the first microphone and the third microphone.

Abstract: Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.

Abstract: Aspects of the embodiments are directed an analog front end circuit (AFE circuit), the AFE circuit including a beamforming circuit configured to receive as an input a plurality of receiver inputs, the receiver inputs coupled to a sensor element. The beamforming circuit can include a plurality of receiver sub-circuits, each sub-circuit including a digital-to-analog converter, a low noise amplifier, and an I/Q mixer circuit element; an adder circuit element at an output of the I/Q mixer circuit element; and a multiplexer coupled to an output of the adder circuit. The AFE can be part of a current sensing device. The current sensing device can include a two-dimensional array of sensor elements.

Abstract: Apparatus and methods for providing an ultra-low power voltage converter are provided. In an example, a method can include receiving an ultra-low power command at a voltage regulator circuit from a load, disabling charge transfer of a regulator of the regulator circuit during an ultra-low power mode of operation in response to a first state of the ultra-low power command, detecting a change in the low power command or in a timeout signal, receiving an indication that the output voltage of the regulator is below a low voltage threshold in response to the change, discharging the output voltage of the regulator for a reset interval in response to the indication, and enabling charge transfer of the regulator after discharging the output voltage.