Patents Assigned to Ansys, Inc.
  • Patent number: 11074763
    Abstract: Machine assisted system and method for changing the shape of a faceted surface using points that move in their local coordinate system collectively are described. The method can include receiving a model having a predefined faceted geometry, the model representing a physical structure that is designed or simulated in a data processing system; generating points surrounding the predefined faceted geometry to be morphed; automatically assigning each of the generated points a respective local coordinate system; selecting a control point among the generated points for controlling a movement of the generated points; and displacing the selected control point in a local coordinate system assigned to the selected control point to cause each point to move based on movement of the selected control point according to the assigned local coordinate system, wherein the displacement of the selected control point guides a morphing of the predefined faceted geometry in the model.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 27, 2021
    Assignee: ANSYS, INC.
    Inventor: Sourabh Chadha
  • Patent number: 11042681
    Abstract: A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of Mi . . . j states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering MN*j combinations. Related apparatus, systems, techniques and articles are also described.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 22, 2021
    Assignee: Ansys, Inc.
    Inventors: John Lee, Aveek Sarkar, Altan Odabasi, Scott Johnson, Murat Becer, William Mullen
  • Patent number: 11035931
    Abstract: Systems and methods are provided for a computer-implemented method for generating a display of radar returns. A geometry data structure is accessed that identifies characteristics of a region of interest including dimensions and movement of one or more objects in the region of interest. A pulse of a plurality of rays is transmitted from an antenna position into the region of interest and the velocities of returns of the rays are captured at a receiver position after the rays have interacted with the one or more objects. Each ray return is assigned into one of a plurality of bins based on the velocity of that ray. A Fourier transform is performed using the binned data to obtain a system response at discrete time intervals. The system response at the discrete time intervals is transformed into Doppler velocity data, and the Doppler velocity data is stored and displayed on a graphical user interface.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 15, 2021
    Assignee: Ansys, Inc.
    Inventor: Robert Kipp
  • Patent number: 10990713
    Abstract: Systems and methods are provided for generating a state space model of a physical system. A matrix decomposition module is configured to receive input data and determine a size of an input matrix based on the input data. When the input matrix size is below a threshold, a singular value decomposition of the input matrix is determined using a first technique. When the input matrix size is above the threshold the input matrix is subdivided into a plurality of subparts. For each subpart, a separability value of that subpart is determined. When the separability value indicates that the subpart is well separated, a singular value decomposition of that subpart is determined using a second technique. When the separability value indicates that the subpart is not well separated, data associated with that subpart is provided to the matrix decomposition module via a recursive call.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 27, 2021
    Assignee: Ansys, Inc.
    Inventor: Amit Hochman
  • Patent number: 10990731
    Abstract: This disclosure describes methods, systems and media for analyzing voltage drops in a power delivery network in a simulated design of an electrical circuit. In one embodiment, a system determines, for a victim element (“victim”), a voltage drop caused by each aggressor element (“aggressor”) in a set of aggressors in the design and creates a data structure that includes, for each victim, at least one of: (1) each voltage drop caused by each aggressor in the set of aggressors or (2) a sum of the voltage drops on the victim caused by all of the aggressors in the set of aggressors. The system can then compute a set of simulations based on random inputs to generate a distribution of possible voltage drops for each victim using data in the data structure.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 27, 2021
    Assignee: ANSYS, INC.
    Inventors: Altan Odabasi, Emrah Acar, Sudarsana Reddy Mallu, Tinu Thomas, Mirza Milan, Scott Johnson, Joao Geada
  • Patent number: 10984163
    Abstract: Systems and methods are provided for performing parallel transient simulations for an electrical circuit. A plurality of segments are generated from a simulation length, and simulations are performed using a plurality of processors for the segments to generate simulation results. An output is generated based at least in part on the simulation results.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 20, 2021
    Assignee: ANSYS, INC.
    Inventor: Ehsan Rasekh
  • Patent number: 10970437
    Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: April 6, 2021
    Assignee: ANSYS, Inc
    Inventors: Hsiming Pan, Zhigang Feng, Norman Chang
  • Patent number: 10963607
    Abstract: Computer-implemented systems and methods are described herein for determining mechanical properties of an electronic assembly. An input specification for a model of the electronic assembly is received, wherein the input specification includes a compressible body and a surrounding component in the electronic assembly. A geometric interference between the compressible body and the surrounding component is identified. A displacement is generated for the compressible body to account for the geometric interference. A non-linear contact is then generated between the displaced compressible body and the surrounding component. The model is updated with the displacement and the non-linear contact. Then, a resulting force equilibrium is determined within the electronic assembly based on the updated model, wherein the resulting force equilibrium is determined by removing the displacement from the updated model.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 30, 2021
    Assignee: Ansys, Inc.
    Inventor: Abel Ramos
  • Patent number: 10872185
    Abstract: Example systems and methods are disclosed for estimating wire capacitance in an RTL circuit design. In an embodiment, a reference post-layout design is received from a non-transitory storage medium, and gate-level nets within the reference post-layout design are classified as either long nets or short nets based, at least in part, on an average fanout length within the gate-level net. A parasitic model may be generated for each of the gate-level nets, and the gate-level nets and associated parasitic models may be stored within either a long net database or a short net database based on the classification of the gate-level net. A net from the RTL circuit design may be classified as either long or short based, at least in part, on a number of modules crossed by one or more fanouts within the net. If the net from the RTL circuit design is classified as long, then capacitance for the net may be estimated using a parasitic model selected from the long net database.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 22, 2020
    Assignee: Ansys, Inc.
    Inventors: Seema Naswa, Praveen Singhal, Paul Traynar
  • Patent number: 10867442
    Abstract: Systems and methods are provided herein for remedying edge and/or face defects of a geometric model. The geometric model of a physical object is received for modeling. The geometric model includes model edges. Each edge is segmented into segments according to a grid having cells overlaid onto the geometric model. A respective centroid of each respective cell is having a segmented edge within the respective cell is determined. A current cell adjacent to an adjacent cell in the grid is identified. The current cell has a segmented edge. A centroid of the current cell is connected with a centroid of the adjacent cell to generate a refined segmented edge. The refined segment is projected onto a corresponding model edge to generate a projected edge. A refined model having one or more projected edges is provided to a graphical user interface for further model characterization of the physical object.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 15, 2020
    Assignee: Ansys, Inc.
    Inventor: Youngkyu Lee
  • Patent number: 10860761
    Abstract: Example systems and methods are disclosed for estimating power consumption by a clock tree in a register-transfer level (RTL) circuit design based on a previously generated reference gate-level circuit design. A plurality of regions within the clock tree structure of the reference gate-level circuit design are identified, where the plurality of regions are demarcated by one or more clock gating structures. A region-based clock model is generated that includes at least one clock constraint model for each identified region. The region-based clock model is used to synthesize the clock tree in the RTL circuit design for estimating power consumption.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Ansys, Inc.
    Inventors: Renuka Vanukuri, Seema Naswa
  • Patent number: 10839123
    Abstract: Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit design is received, the integrated circuit design including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit design based on a vulnerability metric of the vulnerable cell. A power analysis of a portion of the integrated circuit design is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Ansys, Inc.
    Inventors: Joao Geada, Nick Rethman, Ankur Gupta
  • Patent number: 10832474
    Abstract: Systems and methods are provided for generating a tetrahedral mesh representation of a volumetric object. A triangular surface mesh is received that defines a volumetric region. In response to the receiving, a root box is divided into a plurality of partitions with subdivision planes separating adjacent partitions, the triangular surface mesh enclosed within the root box. The plurality of partitions are assigned to different ones of a plurality of mesh processors. A tetrahedral mesh is generated within each of the plurality of partitions. Tetrahedrals that intersect the subdivision planes separating adjacent partitions are deleted to define gap regions, and a conformal tetrahedral mesh representation of the volumetric object is generated, wherein each of the gap regions is filled with an additional tetrahedral mesh.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 10, 2020
    Assignee: Ansys, Inc.
    Inventor: Jan Ivan Vilhem Frykestig
  • Patent number: 10830836
    Abstract: Systems and methods are provided for analyzing magnetic hysteresis of anisotropic magnetic materials. Magnetic hysteresis loops associated with a local coordinate of a coordinated system based on a magnetic field successively applied to each principal axis with an isotropic vector play model are determined. A relaxation factor associated with the convergence behaviors of estimated solution points is applied along with a correction, either a magnetic field correction or a flux density correction, to determine target points on magnetic hysteresis loops. An error between magnetic hysteresis loops and the estimated solution points is determined. The iteration process continues up to a preset number of iterations with alternating correction schemes based on the determined error.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 10, 2020
    Assignee: Ansys, Inc.
    Inventors: Dingsheng Lin, Ping Zhou, Yang Hu
  • Patent number: 10817631
    Abstract: Computer-implemented systems and methods are provided for modeling a charge pump. A relationship between an output voltage of the charge pump and a loading condition is determined. A frequency-domain analysis is performed at multiple frequencies to determine an impedance function representative of the charge pump's impedance at each of the multiple frequencies. A vector-fitting algorithm is applied to approximate the impedance function using a plurality of poles and residues. A circuit is synthesized based on the plurality of poles and residues. A model for the charge pump is generated, where the model includes the synthesized circuit and components that model the relationship between the output voltage and the loading condition.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: October 27, 2020
    Assignee: Ansys, Inc.
    Inventors: Deqi Zhu, Yi Cao, Shan Wan, Norman Chang
  • Patent number: 10803218
    Abstract: Systems and methods are provided for simulating quantile behavior of a physical system. A plurality of parameter samples to a physical system are accessed and a subset of the parameter samples are identified, each of the plurality of parameter samples including a variation of parameters for the physical system. The physical system is simulated based on the subset of the parameter samples to generate simulation results, each of the subset of the parameter samples corresponding to a respective one of the simulation results. A neural network is trained to predict the simulation results based on the subset of the parameter samples.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 13, 2020
    Assignee: ANSYS, INC
    Inventors: Qian Shen, Joao Geada, Robert Geada
  • Patent number: 10803661
    Abstract: Systems and methods are provided for the refining and coarsening of a polyhedra mesh. The refinement includes identifying a plurality of polyhedral cells within a polyhedra mesh. A plurality of parent faces having a plurality of parent face edges are extracted for each polyhedral cell within the polyhedra mesh. For each parent face, a plurality of nodes are defined and connected either isotropically or anisotropically. A plurality of non-overlapping child faces are generated with a perimeter defined by a combination of parent face edges and child face edges. A plurality of child cells are generated from the connection of child faces of the plurality of non-overlapping child faces. Subsequent coarsening of the plurality of child cells occurs by the simultaneous agglomeration into each respective parent cell.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 13, 2020
    Assignee: Ansys, Inc.
    Inventors: Sandeep Menon, Thomas Gessner
  • Patent number: 10786849
    Abstract: Systems and methods are provided for receiving, by a simulation model, a thermal gradient and a cooling rate associated with a 3D printing material as inputs for the simulation model. The systems and methods further include generating, by the simulation model executed by a processing system, characteristics associated with the 3D printing material as outputs of the simulation model based on the thermal gradient and the cooling rate associated with the 3D printing material.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 29, 2020
    Assignee: ANSYS, INC.
    Inventor: Javed Akram
  • Patent number: D916099
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Ansys, Inc.
    Inventors: Frank Edward DeSimone, Samuel Chi-Ngong Mark, Muhammad Rafiuddin, Gregory Mark Alldredge, Sanjaykumar Ranganayakulu
  • Patent number: D916100
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Ansys, Inc.
    Inventors: Frank Edward DeSimone, Glyn Russell Jarvis, Sanjaykumar Ranganayakulu, Jared Anthony Pryor, Andrea Woolfe Felix, Gregory Mark Alldredge, Richard Franklin Kutz