Abstract: An iterative method for calculating and positioning a rectangular balloon containing information in an interactive environment with sensitive areas. A balloon is positioned near, but not overlapping, the sensitive areas of a display screen and is sized based on the amount information to be displayed in the balloon. Each balloon has a body and a tip extending towards the sensitive area. The balloon's position and size is calculated by first initializing the balloon to a preferred variant. If the body does not fit entirely on the screen, a new tip orientation and body is selected while maintaining a golden ratio of height and width. In addition, a new body and tip orientation is selected that displays the largest amount of information if the body does not entirely fit on the display screen.
Abstract: Apparatus for switching data to a bus including apparatus for driving a bus to a first data receiving condition during a first clock period, apparatus for driving the bus to a second data awaiting condition during a second clock period, apparatus for releasing the bus from the second data awaiting condition during the second clock period, and apparatus for maintaining the bus in the second data awaiting condition.
Abstract: The level shifter provides a selective voltage level shift to a common mode signal level on a twisted pair signal line. The level shift is selectively performed based upon the input level of the common mode voltage. The level shifter is advantageously employed in a low voltage circuit wherein lacking sufficient voltage head room to accommodate a constant common mode level shift. An exemplary embodiment is described wherein the level shifter is employed within a bus transceiver of a bus system employing IEEE P1394 bus protocol. In the exemplary embodiment, the selective level shift is applied only to bus signals occurring during an idle phase and an arbitration phase, with no level shift performed during a data phase.
Abstract: A method and apparatus for aligning an optical lens to the imaging array of an imaging system is disclosed. An integrated circuit die implements an imaging circuit and at least one z-height bump. An optical lens formed by injection molding has a lens portion for focusing an image onto the imaging circuit and an alignment portion for engaging the z-height bumps. A tape automated bonding tape carries the integrated circuit die and is aligned to the optical lens.
Type:
Grant
Filed:
August 22, 1994
Date of Patent:
June 13, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Eoin P. O'Regan, Paul A. Coburn, Robert P. Nash, Pat T. O'Donnell, Peter B. Denyer
Abstract: A technique is provided for substantially reducing clicks and pops caused by power cycling, in particular, the power cycling conservation strategy used in a portable computer. More specifically, an audio amplifier arrangement for a computer, in accordance with one embodiment of the present invention, includes a differential amplifier having a first input terminal, a second input terminal and an output terminal. A sound output connector may be connected to the output terminal through a signal path. First switching circuitry is responsive to a first mute signal for connecting together the first input terminal and the second input terminal through a low-impedance path. As a result, an output signal produced by the differential amplifier is essentially forced to zero. When power is removed from or applied to the differential amplifier, however, its behavior is not entirely predictable, and the output signal produced cannot be guaranteed to remain zero throughout the power-down transition.
Type:
Grant
Filed:
February 2, 1994
Date of Patent:
June 13, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Lawrence F. Heyl, Mark C. Gurries, Steven E. Austin
Abstract: The use of a single metal mounting frame within an LCD assembly having an outer plastic housing provides for a thin, light, rigid, and less expensive LCD assembly. The metal mounting frame is coupled to a bezel and aligns an LCD panel between the bezel and the mounting frame. A backlighting assembly which provides illumination for the LCD panel is aligned by the mounting frame and the bezel and is aligned between the mounting frame and a plastic cover panel. The plastic cover panel couples to the bezel to form the outer housing of the LCD assembly.
Type:
Grant
Filed:
October 14, 1992
Date of Patent:
June 6, 1995
Assignee:
Apple Computer, Inc.
Inventors:
William J. Lewis, William J. Schonfeld, Robert Ricommini, Vijay Char
Abstract: An integrated AC adapter and battery charger is disclosed. The apparatus comprises an AC adapter unit for converting AC power to a DC power and a battery charging apparatus coupled to the AC adapter unit for charging a battery pack. The battery charging apparatus further comprises a microcontroller for sensing the condition of the battery pack or tacks being charged, a memory for storing the proper charging profile for a number of different types of battery packs, and a charging current generator capable of generating a varying charging current based on the microcontroller's determination of the battery's condition and the charging profile stored in the memory.
Type:
Grant
Filed:
June 30, 1992
Date of Patent:
May 30, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Andrew Hargadon, Steven J. Young, Kihachiro Tonomura, Markus Wallgren, Mark Gurries
Abstract: A CMOS differential twisted-pair driver which utilizes CMOS switches and current sources advantageously. No alternative power supply is required, the switches do not have to be low impedance and the device is low power. The preferred embodiment driver further limits signal overshoot and common mode energy. The signal transmission facility is bi-directional so an off state is provided. It is doubly terminated to provide for symmetry, improved bandwidth and reduces reflective signal noise. The double termination also provides for faster rise and fall times which reduces the systems sensitivity to receiver offset.
Abstract: A computer system for rendering text is provided. A keyboard is used to enter characters into the computer system. A character code corresponding to each entered character is generated. A particular font is chosen from a font table stored in memory. The font table contains a number of different fonts, with each font having a number of glyph indexes corresponding to a number of different glyphs. A character can have a plurality of different glyph indexes for a particular font. A processor maps the character code to a glyph index according to the selected font and later processes the glyph index. The glyph corresponding to the processed glyph index is then displayed.
Abstract: An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.
Type:
Grant
Filed:
March 16, 1993
Date of Patent:
May 2, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Roger Van Brunt, Daniel L. Hillman, Christopher Nilson, Florin Oprescu, Michael D. Teener
Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal.
Abstract: A circuit for translating data in one of a plurality of data formats into data in any of the other of the plurality of the data formats including apparatus for storing data from a first number of input bytes of data, apparatus for selecting unused bytes from the first number of data bytes stored by the apparatus for storing data and from a second number of input bytes of data, apparatus for placing the unused bytes selected in numerical byte order, and apparatus for placing the data in the numerical byte order in byte position for transfer to the format of a destination device.
Type:
Grant
Filed:
December 30, 1991
Date of Patent:
April 25, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Steven G. Roskowski, Charles M. Flaig, Dean M. Drako
Abstract: This invention provides a method for connecting a mobile computer to a computer network by using an address server. The mobile computer connects itself to a network and requests an address server to represent it on the network. The address server accepts packets intended for the mobile computer and redirects them to the current actual address of the mobile computer. As the mobile computer moves, it reports its new actual address to the address server, so that packets intended for the mobile computer can be redirected to the new actual address.
Type:
Grant
Filed:
July 5, 1994
Date of Patent:
April 25, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Gregory W. Seitz, Sean J. Findley, Philipp W. Beisel
Abstract: An interpretive language comprises instructions making up part of the first sequence of instructions (a test "script"). The first language comprises a first set of instructions, the first set of instructions causes a first computer system (a "host" in a preferred embodiment) to issue a series of commands to a second computer system (a "target") in order to cause the second computer system to emulate user activity on the second computer system. User activity includes emulating typing text and/or moving a mouse cursor position. The language further comprises a second set of instructions which cause the first computer system to issue a series of commands to the second computer system in order to cause the second computer system to respond to the first computer system with its state. This state includes user interface objects, and applications running in the target, etc.
Type:
Grant
Filed:
August 2, 1994
Date of Patent:
April 25, 1995
Assignee:
Apple Computer, Inc.
Inventors:
Jay A. Jessen, Palanivelu Nagaraian, Sean L. Flynn, James A. Schneider
Abstract: An improved multi-codebook phase-in coding process for coding electronic data wherein for each received electronic input data, the coding process detects whether that input data exceeds a current coding maximum, then selecting a codebook coding method from one or more codebook coding methods in response to detecting whether that input data exceeds the current coding maximum, and then encoding that input data in accordance to the selected codebook coding method to generate a coded output data. A corresponding codebook indicator is inserted into a generated coded output data stream to indicate which codebook method to use to decode the coded output data. During decoding, the decoding process detects for a decode method indicator associated with each encoded input data, and decodes in accordance to a decode method corresponding to the detected decode method indicator to generate a decoded output data.
Abstract: A distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value. Each node system of the present invention comprises a CPU, an input device, a display device, a printer or hard copy device, a given amount of RAM and ROM memory, a data storage device, a local clock, a transmitter/receiver, an antenna, a virtual master clock processor, and a common data bus. The method of the present invention comprises the inclusion of a node's local clock value in a message just prior to transmission over the network, storage of a node's local clock value in RAM after an incoming message has been received, and the calculation of the time delay between the sending node and the receiving node by the virtual master clock processor.
Abstract: A method and apparatus for lossless compression and decompression of video image data. Video data is composed of the RGB, YUV or gray scale (color) information for each pixel of each frame of the video data. Storage of such video data can require large amounts of data. The present invention provides for lossless compression and decompression of the individual frames of video image data. Each individual frame of video image data is processed in n.times.n pixel blocks. The combination of colors (called the color list) and the number of different colors in the pixel block is then determined. If the number of colors is above a predetermined threshold, no compression occurs. If the number of colors is below a predetermined threshold, searches for prior occurrences of the combination of colors is than performed. In some instances, a color list for contiguous pixel blocks will be the same. In this instance, a pixel map representing the positioning of the colors in the pixel block is output.
Abstract: An apparatus for emulation routine control transfer creates a jump host instruction (JHI) containing the address of a next emulation routine during the execution of a current emulation routine and outputs the JHI at the end of current emulation routine for transfer of host processor control. The apparatus preferably comprises: an emulated program counter (EPC), a summing means, a state machine, a pointer storage means, an opcode storage means, and a jump instruction circuit. The state machine is preferably coupled to control the loading of the EPC, the loading of the opcode storage means, the summing means, the pointer storage means and the operation of the jump instruction circuit. The pointer storage means is preferably coupled between the data bus and the jump instruction circuit.