Abstract: The present disclosure is directed towards polishing modules for performing chemical mechanical polishing of a substrate. The substrate may be a semiconductor substrate. The polishing modules described have a plurality of pads, such as polishing pads, disposed within a single polishing station. The pads are configured to remain stationary during processing, such as during polishing or buff operations. Either an x-y gantry assembly or a head actuation assembly is coupled to a system body of a polishing module and is configured to move a carrier head over the pads. Between process operations the polishing pads may be indexed to expose a new polishing pad to the carrier head.

Abstract: A polishing system includes a carriage arm having an actuator disposed on a lower surface thereof. The actuator includes a piston and a roller coupled to a distal end of the piston. The polishing system includes a polishing pad and a substrate carrier suspended from the carriage arm and configured to apply a pressure between a substrate and the polishing pad. The substrate carrier includes a housing, a retaining ring, and a membrane. The substrate carrier includes an upper load ring disposed in the housing. The roller of the actuator is configured to contact the upper load ring during relative rotation between the substrate carrier and the carriage arm. The actuator is configured to apply a load to a portion of the upper load ring thereby altering the pressure applied between the substrate and the polishing pad.

Abstract: A method for removing etchant byproduct from an etch reactor and discharging a substrate from an electrostatic chuck of the etch reactor is provided. One or more layers on a substrate electrostatically secured to an electrostatic chuck within a chamber of the etch reactor is etched using a first plasma, causing an etchant byproduct to be generated. A portion of the one or more layers are covered by a photoresist. After the etching is complete, a second plasma is provided into the chamber for a time period sufficient to trim the photoresist and remove a portion of the etchant byproduct. A second time period sufficient to electrostatically discharge the substrate using the second plasma is determined. Responsive to deactivating one or more chucking electrodes of the electrostatic chuck, the second plasma is provided into the chamber for the second time period and the substrate is removed from the chamber.

Abstract: The disclosure describes devices, systems and methods relating to a transfer chamber for an electronic device processing system. For example, a method includes causing a robot arm to pick up a substrate. The robot arm is caused to pick up the substrate by causing a first mover to rotate or to change a first distance to a second mover. Rotation of the first mover or the change in the first distance causes the first robot arm to rotate about a shoulder axis. The robot arm is further caused to pick up the substrate by causing one of a) a second mover to rotate or b) a third mover to change a second distance to the second mover. Rotation of the second mover or the change in the second distance causes the robot arm to raise or lower.

Abstract: A support device includes a substrate receiving region. The support device includes a support body shaped as a pattern having an array of openings. The support body is a sparse structure wherein a joint area of the openings of the array of openings is 40% or more of the area of the substrate receiving region. The support body includes one or more suction openings configured to be in fluid communication with a vacuum source arrangement.

Abstract: Methods for monitoring process chambers using a controllable plasma oxidation process followed by a controlled reduction process and metrology are described. In some embodiments, the metrology comprises measuring the reflectivity of the metal oxide film formed by the controllable plasma oxidation process and the reduced metal film or surface modified film formed by reducing the metal oxide film.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-? dielectric layer after the annealing process (in dipole last processes).

Abstract: A support unit for supporting a supported element, including (a) a spherical joint, (b) a pressure applying unit that is configured to maintain contact between a spherical outer surface and a base, (c) a position control unit that is configured to contact the spherical joint positioning element at multiple contact points and to set values of a first angle of rotation and a second angle of rotation of the spherical outer surface. The spherical joint is located above the position control unit. A distance between a fixed center of rotation and a point on the spherical outer surface is smaller than (b) a distance between the fixed center of rotation and any contact point of the multiple contact points.

Abstract: Methods of depositing improved quality silicon nitride (SixNy) films are disclosed. Exemplary methods include exposing a semiconductor substrate in a semiconductor processing chamber to a silicon-containing precursor, to a first plasma produced from a first gas mixture comprising helium (He) and nitrogen (N2), the first gas mixture comprising a ratio of helium:nitrogen in a range of from 20:1 to 1000:1, and exposing the semiconductor substrate to a second plasma produced from a second gas mixture comprising helium (He), nitrogen (N2), and ammonia (NH3).

Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

Abstract: Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in the annular member between interior surfaces of the walls. A divider may be disposed within the plenum, where the divider separates the plenum into a first plenum chamber and a second plenum chamber, wherein the first plenum chamber is fluidly accessible from the apertures defined through the inner wall, and wherein the divider defines at least one aperture providing fluid access between the first plenum chamber and the second plenum chamber.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a middle sacrificial layer on a top surface of the first hGAA structure, the middle sacrificial layer comprising silicon germanium (SiGe); and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise silicon germanium (SiGe).

Abstract: Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include removing at least a portion of the metal-containing hardmask material.

Abstract: Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.

Abstract: Embodiments of the present disclosure generally relate to methods of forming a substrate having a target thickness distribution at one or more eyepiece areas across a substrate. The substrate includes eyepiece areas corresponding to areas where optical device eyepieces are to be formed on the substrate. Each eyepiece area includes a target thickness distribution. A base substrate thickness distribution of a base substrate is measured such that a target thickness change can be determined. The methods described herein are utilized along with the target thickness change to form a substrate with the target thickness distribution.

Abstract: A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.

Abstract: Methods and apparatus for controlling plasma in a process chamber leverage an RF termination filter which provides an RF path to ground. In some embodiments, an apparatus may include a DC filter configured to be electrically connected between a DC power supply and electrodes embedded in an electrostatic chuck where the DC filter is configured to block DC current from the DC power supply from flowing through the DC filter and an RF termination filter configured to be electrically connected between the DC filter and an RF ground of the process chamber where the RF termination filter is configured to adjust an impedance of the electrodes relative to the RF ground.

Abstract: A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Abstract: Provided herein are approaches for providing a more uniform ion flux and ion angular distribution across a wafer to minimize etch yield loss resulting from etch profile variations. In some embodiments, a system may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, wherein the plasma source comprises a plasma shaper extending into the plasma chamber from a wall of the chamber housing. The plasma shaper may include a shaper wall coupled to the wall of the chamber housing, and a shaper end wall connected to the shaper wall, the shaper end wall defining an indentation extending towards the wall of the chamber housing.