Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the ultimate tensile strength and the elongation at break is greater than or about 2,000.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a bottom plate coupled with a bottom surface of the chamber body. The chambers may include a substrate support assembly disposed within the chamber body. The substrate support assembly may include a support plate and a support stem coupled with the support plate. The chambers may include a mounting bracket that couples the support stem with a lower surface of the bottom plate. The chambers may include a plurality of tilt actuators. Each of the tilt actuators may couple the mounting bracket with the lower surface of the bottom plate. Each of the tilt actuators may be operable to adjust a vertical distance between the lower surface of the bottom plate and the mounting bracket at a mounting site of the respective tilt actuator to adjust a planarity of the support plate relative to the bottom plate.

Abstract: Methods of semiconductor processing may include forming plasma effluents of a hydrogen-and-fluorine-containing precursor. The plasma effluents may then contact a silicon-containing hardmask material and a photoresist material. The silicon-containing hardmask material can overlay an organic material overlaying a substrate in a processing region of a semiconductor processing chamber. Etching the silicon-containing hardmask material with the plasma effluents while the photoresist material with the plasma effluents. The silicon-containing hardmask material can be etched at a selectivity greater than or about 10 relative to the photoresist material. A temperature in the processing region can be maintained at about ?20° C. or less.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Exemplary chemical mechanical cleaning systems may include a carrier head. The systems may include a motor that is coupled with the carrier head. The motor may be operable to rotate the carrier head about a central axis of the carrier head. The systems may include a two-stage downforce actuator that is operable to vertically translate the carrier head and the motor between a raised position and a cleaning position. The downforce actuator may include a first stage that includes a linear actuator that is operable to vertically translate the carrier head between the raised position and at least an upper 50% of a vertical travel distance between the raised and cleaning positions. The downforce actuator may include a second stage that includes an expandable flexure that is operable to vertically translate the carrier head between the cleaning position and no greater than a lower 50% of the vertical distance.

Abstract: Exemplary electroplating systems may include a vessel. The systems may include a head that is configured to hold a substrate. The head may be positionable within an interior of the vessel. The systems may include a spray jet array disposed within the interior of the vessel. The spray jet array may include a plate defining a plurality of apertures through a thickness of the plate. The systems may include at least one fluid pump that is fluidly coupled with an inlet end of each of the plurality of apertures.

Abstract: A system may include a gimbal defining a plurality of pockets, where each pocket may include a first portion and a second portion that extends between the first portion and a base of the pocket. The second portion may have a greater diameter than the first portion. The system may include a plurality of conditioning disks, where each conditioning disk is seated within the first portion of a respective pocket. The system may include a plurality of gaskets, where each gasket is seated within the second portion of a respective pocket. The system may include a plurality o-rings, each o-ring disposed between a peripheral edge of one of the plurality of conditioning disks and a lateral wall of one of the plurality of pockets. The system may include a plurality of shoulder screws for coupling the gimbal with one of the plurality of gaskets and a conditioning disk.

Abstract: A semiconductor device may include a substrate. The semiconductor device may also include a dielectric material characterized, at least in part, by a dielectric constant. The semiconductor device may include a metallic pathway formed in the dielectric material. The semiconductor device may include a region about the metallic pathway of the semiconductor device may include a plurality of air gaps within the dielectric material and arranged three-dimensionally throughout the region, where the region may include a lower dielectric constant than the dielectric constant of the dielectric material.

Abstract: An electronic device manufacturing system includes a mainframe including a transfer chamber and facets defining side walls of the transfer chamber. The facets include first facet, second facet, third facet, and fourth facet that form the transfer chamber. The first facet has a first number of substrate access ports. The second facet has a second number of substrate access ports. A first substrate access port of the first facet has a first side dimension and a second substrate access port of the second facet has a second side dimension that is different from the first side dimension. The second facet is adjacent to the first facet. The third facet is adjacent to the second facet. The fourth facet has the second number of substrate access ports. The second number of substrate access ports is different than the first number of substrate access ports.

Abstract: There is provided a system of examination of a semiconductor specimen, comprising a processor and memory circuitry configured to obtain, for each given candidate defect of a plurality of candidate defects in an image of the specimen, a given area of the given candidate defect in the image, obtain a reference image, perform a segmentation of at least part of the reference image, to determine, for each given candidate defect, first reference areas in the reference image matching a given reference area corresponding to the given area, select among the first reference areas, a plurality of second reference areas, obtain a plurality of corresponding second areas in the image, and use data informative of a pixel intensity of the second areas and data informative of a pixel intensity of the given area to determine whether the given candidate defect corresponds to a defect.

Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.

Abstract: A method of deposition on a substrate used for the manufacture of a solar cell is provided. The method includes depositing a first conductive pattern on a first side of the substrate. The first conductive pattern is one of a plurality of busbars and a plurality of fingers. The method includes providing a screen over the substrate. The screen includes a set of openings. The screen has a bottom side having a varying vertical profile including low portions and high portions. The method includes transferring a printing material from the screen to the substrate through the set of openings to print a second conductive pattern on the first side of the substrate. The second conductive pattern is the other one of the plurality of busbars and the plurality of fingers. During the printing of the second conductive pattern, the first conductive pattern is substantially wet and the screen is disposed over the substrate in a manner such that the high portions are elevated above the first conductive pattern.

Abstract: Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.

Abstract: The enclosed disclosure relates to a method and apparatus for depositing functionalized nanoparticles within a semiconductor structure in order to create a nano-layer capable of enhancing imaging and contrast, The semiconductor structure can include any type of VNAND structure or 3D structure, The nanoparticles are formed in high-aspect ratio trenches of the structure and form a nano-layer. The functionalized nanoparticles comprise synthesized nanoparticles as well as organic molecules. The organic molecules are chosen to selectively bind to certain nanoparticles and surface materials.

Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources and plasma processing apparatus. In at least one embodiment, plasma source includes a first sidewall and a gas injection insert defining a plasma source interior volume. The gas injection insert includes a peripheral gas injection port, a second sidewall disposed concentric with the first sidewall, and a center gas injection port. The plasma source includes a first induction coil disposed proximate the first sidewall and disposed around the first sidewall. The plasma source includes a first radio frequency power generator coupled with the first induction coil. The plasma source includes a second induction coil disposed proximate the second sidewall and disposed around the second sidewall. The plasma source includes a second radio frequency power generator coupled with the second induction coil.

Abstract: A neural network is trained for use in a substrate residue classification system by obtaining ground truth residue level measurements of a top layer of a calibration substrate at a plurality of locations, each location at a defined position for a die being fabricated on the substrate. A plurality of color images of the calibration substrate are obtained, each color image corresponding to a region for a die being fabricated on the substrate. A neural network is trained to convert color images of die regions from an in-line substrate imager to residue level measurements for the top layer in the die region.

Abstract: A method of evaluating a region of interest of a sample including: positioning the sample within in a vacuum chamber of an evaluation tool that includes a scanning electron microscope (SEM) column and a focused ion beam (FIB) column; acquiring a plurality of two-dimensional images of the region of interest by alternating a sequence of delayering the region of interest with a charged particle beam from the FIB column and imaging a surface of the region of interest with the SEM column; generating an initial three-dimensional data cube representing the region of interest by stacking the plurality of two-dimensional images on top of each other in an order in which they were acquired; identifying distortions within the initial three-dimensional data cube; and creating an updated three-dimensional data cube that includes corrections for the identified distortions.

Abstract: A method and apparatus for growing an oxide layer within a feature of a substrate is described herein. The method is suitable for use in semiconductor manufacturing. The oxide layer is formed by exposing a substrate to both a high pressure oxidant exposure and a lower pressure oxygen containing plasma exposure. The high pressure oxidant exposure is performed at a pressure of greater than 10 Torr, while the lower pressure oxygen containing plasma exposure is performed at a pressure of less than about 10 Torr. The features are high-aspect ratio trenches or holes within a stack of silicon oxide and silicon nitride layers.

Abstract: An advanced temperature control system and method are described for a wafer carrier in a plasma processing chamber. In one example a heat exchanger provides a temperature controlled thermal fluid to a fluid channel of a workpiece carrier and receives the thermal fluid from the fluid channel. A proportional valve is between the heat exchanger and the fluid channel to control the rate of flow of thermal fluid from the heat exchanger to the fluid channel. A pneumatic valve is also between the heat exchanger and the fluid channel also to control the rate of flow of thermal fluid from the heat exchanger and the fluid channel. A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve and the pneumatic valve in response to the measured temperature to adjust the rate of flow of the thermal fluid.