Abstract: Extreme ultraviolet (EUV) mask blanks, production systems therefor, and methods of increasing multilayer film reflectance are disclosed. The EUV mask blanks comprise a bilayer film on a substrate. The bilayer film comprises a first film layer including silicon (Si), and a second film layer comprising an element selected from the group consisting of ruthenium (Ru), nickel (Ni), cobalt (Co), tungsten (W), iron (Fe), titanium (Ti) and silicides thereof. Some EUV mask blanks further comprise a multilayer reflective stack comprising alternating layers on the bilayer film and a capping layer on the multilayer reflective stack. Some EUV mask blanks include a smoothing layer selected from the group consisting of molybdenum silicide (MoSi), boron carbide (B4C) and silicon nitride (SiN) on the multilayer reflective stack, a capping layer on the smoothing layer, and an absorber layer on the capping layer.

Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a substrate housed in the processing region of the semiconductor processing chamber. The methods may include halting a flow of the carbon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the carbon-containing material with plasma effluents of an oxidizing material. The methods may include forming volatile materials from a surface of the carbon-containing material.

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: A method reduces differences in chucking forces that are applied by two electrodes of an electrostatic chuck, to a substrate disposed atop the chuck. The method includes providing initial chucking voltages to each of the two electrodes, and measuring an initial current provided to at least a first electrode of the two electrodes. The method further includes initiating a process that affects a DC voltage of the substrate, then measuring a modified current provided to at least the first electrode, and determining, based at least on the initial current and the modified current, a modified chucking voltage for a selected one of the two electrodes, that will reduce chucking force imbalance across the substrate. The method also includes providing the modified chucking voltage to the selected one of the two electrodes.

Abstract: A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

Abstract: Methods, systems, and non-transitory computer readable medium are described for sensor metrology data integration. A method includes receiving sets of sensor data and sets of metrology data. Each set of sensor data includes corresponding sensor values associated with producing corresponding product by manufacturing equipment and a corresponding sensor data identifier. Each set of metrology data includes corresponding metrology values associated with the corresponding product manufactured by the manufacturing equipment and a corresponding metrology data identifier. The method further includes determining common portions between each corresponding sensor data identifier and each corresponding metrology data identifier. The method further includes, for each of the sensor-metrology matches, generating a corresponding set of aggregated sensor-metrology data and storing the sets of aggregated sensor-metrology data to train a machine learning model.

Abstract: One embodiment of the disclosure provides a method of fabricating a chamber component with a coating layer disposed on an interface layer with desired film properties. In one embodiment, a method of fabricating a coating material includes providing a base structure comprising an aluminum or silicon containing material, forming an interface layer on the base structure, wherein the interface layer comprises one or more elements from at least one of Ta, Al, Si, Mg, Y, or combinations thereof, and forming a coating layer on the interface layer, wherein the coating layer has a molecular structure of SivYwMgxAlyOz. In another embodiment, a chamber component includes an interface layer disposed on a base structure, wherein the interface layer is selected from at least one of Ta, Al, Si, Mg, Y, or combinations thereof, and a coating layer disposed on the interface layer, wherein the coating layer has a molecular structure of SivYwMgxAlyOz.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.

Abstract: An apparatus may include a drift tube assembly, arranged to transmit an ion beam. The drift tube assembly may include a first ground electrode; an RF drift tube assembly, disposed downstream of the first ground electrode; and a second ground electrode, disposed downstream of the RF drift tube assembly. The RF drift tube assembly may define a triple gap configuration. The apparatus may include a resonator, where the resonator comprises a toroidal coil, having a first end, connected to a first RF drift tube of the RF drift tube assembly, and a second end, connected to a second RF drift tube of the RF drift tube assembly.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer comprising an alloy of molybdenum (Mo) and antimony (Sb).

Abstract: Inspection data that corresponds to potential defects of an object may be received. A first set of locations of first potential defects can be identified. The first set of locations of the first potential defects can be imaged with a review tool to obtain a first set of review images. The first potential defects can be classified based on the first set of review images to obtain first classification results of the first potential defects. An instruction can be determined for the review tool based on the first classification results, the instruction being associated with detecting potential defects. Using the instruction, a second set of locations of second potential defects of the plurality of potential defects to be imaged with the review tool can be identified.

Abstract: Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Abstract: The present disclosure relates to a support ring for a thermal processing chamber. The support ring has a polysilicon coating. The polysilicon coating is formed using a plasma spray deposition process.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining a transfer region fluidly coupled with a plurality of processing regions. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a transfer apparatus having a central hub including a shaft extending at a distal end through the transfer region housing into the transfer region. The transfer apparatus may include a lateral translation apparatus coupled with an exterior surface of the transfer region housing, and configured to provide at least one direction of lateral movement of the shaft. The systems may also include an end effector coupled with the shaft within the transfer region. The end effector may include a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports in the transfer region.

Abstract: A method of modifying a high-resistivity substrate so that the substrate may be electrostatically clamped to a chuck is disclosed. The bottom surface is implanted with a resistivity-reducing species. In this way, resistivity of the bottom surface of the substrate may be greatly reduced. In some embodiments, to implant the bottom surface, a coating is applied to the top surface. After application of the coating, the substrate is flipped so that the front surface contacts the top surface of the chuck. The ions are then implanted into the exposed bottom surface to create the low resistivity layer. The resistivity of the low resistivity layer proximate the bottom surface after implant may be less than 1000 ohm-cm. Once the bottom surface has been implanted, the substrate may be processed conventionally. The low resistivity layer may later be removed by wafer backside thinning processes.

Abstract: The present disclosure generally relates to methods and systems for manufacturing wire grid polarizers (WGP) using Markle-Dyson exposure systems and dual tone development (DTD) frequency doubling. In one embodiment, the method includes depositing a photoresist layer over an aluminum-coated display substrate, patterning the photoresist layer by dual tone development using a Markle-Dyson system to form a photoresist pattern, and transferring the photoresist pattern into the aluminum-coated display substrate to manufacture a WGP having finer pitch, for example less than or equal to about 100 nm, and increased frequency.

Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency above 15 MHz. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.0.