Abstract: Ampoules for a semiconductor manufacturing precursors and methods of use are described. The ampoules include a container with an inlet port and an outlet port. The ampoules comprise an inlet plenum located between the inlet port and the cavity and an outlet plenum located between the outlet port and the cavity. A flow path is defined by a plurality of tubular walls and an ingress openings of the ampoule, through which a carrier gas flows in contact with the precursor.

Abstract: The disclosure describes devices, systems, and methods for integrating load locks into a factory interface footprint space. A factory interface for an electronic device manufacturing system can include an interior volume defined by a bottom, a top and a plurality of sides, a first load lock disposed within the interior volume of the factory interface, and a first factory interface robot disposed within the interior volume of the factory interface, wherein the first factory interface robot is configured to transfer substrates between a first set of substrate carriers and the first load lock.

Abstract: During chemical mechanical polishing of a substrate, a signal value that depends on a thickness of a layer in a measurement spot on a substrate undergoing polishing is determined by a first in-situ monitoring system. An image of at least the measurement spot of the substrate is generated by a second in-situ imaging system. Machine vision processing, e.g., a convolutional neural network, is used to determine a characterizing value for the measurement spot based on the image. Then a measurement value is calculated based on both the characterizing value and the signal value.

Abstract: An article includes a body having a plasma-sprayed ceramic coating on a surface thereof. The body can be formed of at one least one of the following materials: Al, Al2O3, AlN, Y2O3, YSZ, or SiC. The plasma-sprayed ceramic coating can include at least one of Y2O3, Y4Al2O9, Y3Al5O12 or a solid-solution of Y2O3 mixed with at least one of ZrO2, Al2O3, HfO2, Er2O3, Nd2O3, Nb2O5, CeO2, Sm2O3 or Yb2O3. The plasma-sprayed ceramic coating can further include splats.

Abstract: The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

Abstract: Embodiments disclosed herein comprise a sensor. In an embodiment, the sensor comprises a substrate having a first surface and a second surface opposite from the first surface. In an embodiment, the sensor further comprises a first electrode over the first surface of the substrate, and a second electrode over the first surface of the substrate and adjacent to the first electrode. In an embodiment, the sensor further comprises a barrier layer over the first electrode and the second electrode.

Abstract: Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

Abstract: Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths.

Abstract: A depth measuring apparatus includes a camera assembly configured to capture a plurality of images of a target at a plurality of distances from the target. The depth measuring apparatus further includes a controller configured to, for each of a plurality of regions within the plurality of images: determine corresponding gradient values within the plurality of images; determine a corresponding maximum gradient value from the corresponding gradient values; and determine, based on the corresponding maximum gradient value, a depth measurement for a region of the plurality of regions.

Abstract: Described are memory devices having a metal silicide, resulting in a low resistance contact. Methods of forming a memory device are described. The methods include forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side. A capacitor is then formed on the capacitor side of the metal silicide layer, and a bit line is formed on the bit line side of the metal silicide layer.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Abstract: Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Abstract: Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.

Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

Abstract: A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: An aperture diaphragm capable of varying the size of an aperture in two dimensions is disclosed. The aperture diaphragm may be utilized in an ion implantation system, such as between the mass analyzer and the acceleration column. In this way, the aperture diaphragm may be used to control at least one parameter of the ion beam. These parameters may include angular spread in the height direction, angular spread in the width direction, beam current or cross-sectional area. Various embodiments of the aperture diaphragm are shown. In certain embodiments, the size of the aperture in the height and width directions may be independently controlled, while in other embodiments, the ratio between height and width is constant.

Abstract: Examples of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One example provides a hoop assembly for use in a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein. A hoop body mates with the confinement ring. The hoop body is slanted to reduce a thickness across a diameter of the hoop body. Three or more lifting fingers are attached to the hoop body and extend downwards. Each of the three or more lifting fingers has a contact tip positioned radially inward from the hoop body to form a substrate support surface below and spaced apart from the confinement region.