Abstract: A method and apparatus for processing a semiconductor is disclosed herein. In one embodiment, a processing system for semiconductor processing is disclosed. The processing chamber includes two transfer chambers, a processing chamber, and a rotation module. The processing chamber is coupled to the transfer chamber. The rotation module is positioned between the transfer chambers. The rotation module is configured to rotate the substrate. The transfer chambers are configured to transfer the substrate between the processing chamber and the transfer chamber. In another embodiment, a method for processing a substrate on the apparatus is disclosed herein.

Abstract: A polishing apparatus includes a polishing station to hold a polishing pad, a carrier head to hold a substrate in contact with a polishing pad at the polishing station, a camera positioned to capture an image of a lower surface of a consumable part when the consumable part moves away from the polishing pad, and a controller configured to perform an image processing algorithm on the image to determine whether the consumable part is damaged. The consumable part can be a retaining ring on a carrier head, or a conditioner disk on a conditioner head.

Abstract: Exemplary semiconductor processing methods to clean a substrate processing chamber are described. The methods may include depositing a dielectric film on a first substrate in a substrate processing chamber, where the dielectric film may include a silicon-carbon-oxide. The first substrate having the dielectric film may be removed from the substrate processing chamber, and the dielectric film may be deposited on at least one more substrate in the substrate processing chamber. The at least one more substrate may be removed from the substrate processing chamber after the dielectric film is deposited on the substrate. Etch plasma effluents may flow into the substrate processing chamber after the removal of a last substrate having the dielectric film. The etch plasma effluents may include greater than or about 500 sccm of NF3 plasma effluents, and greater than or about 1000 sccm of O2 plasma effluents.

Abstract: Exemplary substrate processing systems may include a factory interface and a load lock coupled with the factory interface. The systems may include a transfer chamber coupled with the load lock. The transfer chamber may include a robot configured to retrieve substrates from the load lock. The systems may include a chamber system positioned adjacent and coupled with the transfer chamber. The chamber system may include a transfer region laterally accessible to the robot. The transfer region may include a plurality of substrate supports disposed about the transfer region. Each substrate support of the plurality of substrate supports may be vertically translatable. The transfer region may also include a transfer apparatus rotatable about a central axis and configured to engage substrates and transfer substrates among the plurality of substrate supports. The chamber system may also include a plurality of processing regions vertically offset and axially aligned with an associated substrate support.

Abstract: A quantum device includes a substrate including a first material and including an upper surface thereof, a first layer comprising a compound of the first material disposed on the upper surface of the substrate, a second layer, comprising a metal oxide, disposed on the first layer, a third layer, comprising a noble metal, disposed on the second layer, a fourth layer, comprising a metal oxide, disposed on the third layer, a fifth layer, comprising a piezoelectric material, disposed on the fourth layer, a sixth layer, comprising a noble metal, disposed on the fifth layer, a seventh layer, comprising a material capable of quantum emission, disposed on the sixth layer, and an eighth layer, comprising a noble metal, disposed on the seventh layer, and at least one of the eighth layer and the seventh layer are sized to enable quantum emission from the seventh layer.

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.

Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

Abstract: A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible.

Abstract: An electronic device manufacturing system includes a mainframe that includes a first transfer chamber and facets defining first side walls of the first transfer chamber. The facets include a first facet that has a first number of substrate access ports, a second facet that has a second number of substrate access ports, and a third facet that has the second number of substrate access ports. The second number of substrate access ports is different than the first number of substrate access ports.

Abstract: An article comprises a body having a protective coating. The protective coating is a thin film that comprises a metal oxy-fluoride. The metal oxy-fluoride has an empirical formula of MxOyFz, where M is a metal, y has a value of 0.1 to 1.9 times a value of x and z has a value of 0.1 to 3.9 times the value of x. The protective coating has a thickness of 1 to 30 microns and a porosity of less than 0.1%.

Abstract: An apparatus may include global control module, the global control module including a digital master clock generator and a master waveform generator. The apparatus may also include a plurality of resonator control modules, coupled to the global control module. A given resonator control module of the plurality of resonator control modules may include a synchronization module, having a first input coupled to receive a resonator output voltage pickup signal from a local resonator, a second input coupled to receive a digital master clock signal from the digital master clock generator, and a first output coupled to send a delay signal to the master waveform generator.

Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

Abstract: Exemplary semiconductor processing systems may include an inductively coupled plasma source. The systems may include an RF power source that is electrically coupled with the inductively coupled plasma source. The systems may include a first gas source fluidly coupled with the inductively coupled plasma source. The systems may include a second gas source. The systems may include a dual-channel showerhead assembly defining a first plurality of apertures and a second plurality of apertures. The first plurality of apertures may be fluidly coupled with the inductively coupled plasma source. The second plurality of apertures are fluidly coupled with the second gas source.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining an internal volume. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a plurality of substrate supports disposed within the transfer region. The systems may also include a transfer apparatus having a central hub including a first shaft and a second shaft concentric with and counter-rotatable to the first shaft. The transfer apparatus may include a first end effector coupled with the first shaft. The first end effector may include a plurality of first arms. The transfer apparatus may also include a second end effector coupled with the second shaft. The second end effector may include a plurality of second arms having a number of second arms equal to the number of first arms of the first end effector.

Abstract: An article comprises a body and a conformal protective layer on at least one surface of the body. The conformal protective layer is a plasma resistant rare earth oxide film having a thickness of less than 1000 ?m, wherein the plasma resistant rare earth oxide film consists essentially of 40 mol % to less than 100 mol % of Y2O3, over 0 mol % to 60 mol % of ZrO2, and 0 mol % to 9 mol % of Al2O3.

Abstract: Methods of enhancing selective deposition are described. In some embodiments, a passivation layer is deposited on a metal surface before deposition of a dielectric material. A block I molecule is deposited on a metal surface, and a block II molecule is reacted with the block I molecule to form a passivation layer.

Abstract: Deposition methods and apparatus for conditioning a process kit to increase process kit lifetime are described. A nitride film formed on a process kit is exposed to conditioning process comprising nitrogen and hydrogen radicals to condition the nitride film to decrease particulate contamination from the process kit.

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.