Abstract: A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.

Abstract: An equalized-impedance shadowed current cell can be arrayed in a Digital-to-Analog Converter (DAC) or other converters or applications. The Equalized-impedance shadowed current cell has primary differential transistors in parallel with shadow differential transistors that have gates driven inversely to gates of the primary differential transistors. A shadow current from the shadow differential transistors is much smaller than a primary current switched by the primary differential transistors. Cell current is not switched off to zero but to the shadow current. The ON state and OFF state impedances of the current cell may be matched during circuit design so that the impedance is the same regardless of digital input values. The Width and Length of the shadow differential transistors are adjusted so that overall output impedances for the ON and OFF states of the current cell are matched. Since output impedance is input code independent, high-speed performance is improved.

Abstract: An electro-static-discharge (ESD) protection circuit is a power clamp between a high-voltage power supply VDDH and a ground. The power clamp protects high-voltage transistors in a first core and low-voltage transistors in a second core using a low-voltage clamp transistor. The low-voltage transistors have lower power-supply and snap-back voltages than the high-voltage transistors. Trigger circuits are triggered when an ESD pulse is detected on VDDH. One trigger circuit enables a gate of the low-voltage clamp transistor. A series of diodes connected between VDDH and a drain of the clamp transistor prevents latch up or snap-back during normal operation. During an ESD pulse, the series of diodes is briefly bypassed by a p-channel bypass transistor when a second trigger circuit activates an initial trigger transistor which pulses the gate of the p-channel bypass transistor low for a period of time set by an R-C network in the second trigger circuit.

Abstract: A two-stage op amp has a transconductance cell in a second stage modified to match a transconductance cell in a first stage. A transconductance swap network is inserted between transconductance cells and trans-impedance cells, such as current-steering networks, current mirrors, or drivers connected to the transconductance cells. The transconductance swap network directly connects the first transconductance cell to the first stage trans-impedance cell during a second clock phase, but crosses-over the first transconductance cell to the second-stage trans-impedance cell during a first clock phase. A first switched-capacitor network drives the gates of differential transistors in the first transconductance cell by alternately sampling an input and feedback, and equalizing to reset inputs. A second first switched-capacitor network drives differential transistors in the second transconductance cell, but during opposite clock phases.

Abstract: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

Abstract: A two-stage op amp has a transconductance cell in a second stage modified to match a transconductance cell in a first stage. A transconductance swap network is inserted between transconductance cells and trans-impedance cells, such as current-steering networks, current mirrors, or drivers connected to the transconductance cells. The transconductance swap network directly connects the first transconductance cell to the first stage trans-impedance cell during a second clock phase, but crosses-over the first transconductance cell to the second-stage trans-impedance cell during a first clock phase. A first switched-capacitor network drives the gates of differential transistors in the first transconductance cell by alternately sampling an input and feedback, and equalizing to reset inputs. A second first switched-capacitor network drives differential transistors in the second transconductance cell, but during opposite clock phases.

Abstract: A light-emitting diode (LED) driver provides faster rise and fall times for LED current to reduce image sticking and other interference. A standard DC-DC converter provides a sum current that is slowly ramped up and down by a bypass current digital-to-analog converter (DAC). A digital value to the bypass current DAC is ramped up or down before an LED current is turned on or off. When the LED current is turned on, current is shifted from a bypass path to a path through the LED, maintaining a constant sum current from the DC-DC converter. When a different LED is turned on, current is shifted from one LED's path to the other LED's path. Separate LED current DAC's in each LED path and in the bypass path can share the sum current with digital precision. Using a single DAC for the sum current and switches in each path reduces cost.

Abstract: A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.

Abstract: A method of aligning electronic components comprising providing a positioning member 110 having at least one formation 120 for receiving an electronic component; said at least one formation having lateral boundaries 35, 36 for constraining movement of an electronic component; placing a first electronic component 10a in said at least one formation; and providing a force for actively aligning said first electronic component with a lateral boundary of said at least one formation. The force may, for example, be provided by tilting the positioning member, by providing suction or by using an actuator. An apparatus for aligning electronic components and a 3D system of stacked electronic components is also disclosed.

Abstract: An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided.

Abstract: A content distribution method with broadcast encryption, comprising: executing a setup process, comprising: generating public domain parameters, generating a server secret, and generating one or more client private keys, one for each content receiving client; executing an encryption process, comprising: generating a cipher text using the server secret, a subscriber set, and a randomness, the cipher text being constant and independent of total number of content receiving clients in a distribution network, generating a plain text using the server secret and the randomness, encrypting an original content into an encrypted content using the plain text; distributing the client private keys to the content receiving clients; distributing the cipher text to the content receiving clients; broadcasting the encrypted content through the distribution network; and executing a decryption process on the encrypted content by each of the content receiving clients in the distribution network.

Abstract: A frame-rate converter reduces halo artifacts along edges of moving objects. Halo artifacts occur on interpolated frames where a moving object covers and uncovers pixels along its edges. Motion estimation among three original frames produces hybrid direction motion vectors that are bi-directional for background and objects, but are unidirectional for covered and uncovered regions, since motion vectors with large matching errors are deleted. Covered regions in the interpolated frame are detected as intersecting only a forward but no backward hybrid motion vector. Bi-directional motion estimation from the hybrid motion vectors of two original frames produces refined motion vectors for the interpolated frame. Refined motion vectors in the covered regions are deleted and replaced with hybrid motion vectors from the original frames. Hybrid motion vectors from the original frames are assigned to the critical covered regions rather than using interpolated vectors in the covered regions, reducing halo artifacts.

Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Abstract: A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.

Abstract: A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.

Abstract: A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Abstract: A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Abstract: A light-emitting diode (LED) driver provides faster rise and fall times for LED current to reduce image sticking and other interference. A standard DC-DC converter provides a sum current that is slowly ramped up and down by a bypass current digital-to-analog converter (DAC). A digital value to the bypass current DAC is ramped up or down before an LED current is turned on or off. When the LED current is turned on, current is shifted from a bypass path to a path through the LED, maintaining a constant sum current from the DC-DC converter. When a different LED is turned on, current is shifted from one LED's path to the other LED's path. Separate LED current DAC's in each LED path and in the bypass path can share the sum current with digital precision. Using a single DAC for the sum current and switches in each path reduces cost.

Abstract: An electronic or micromechanical device having first (11) and second (12) surfaces and a via extending through the device from the first surface to the second surface. The via comprises integrally formed first (84, 86), second (82) and third (88) portions. The first portion (84, 86) extends from the first surface (11) to the second surface (12). The second portion (82) extends over a part of the first surface (11) of the device. The third portion (88) extends over a part of the second surface (12) of the device. Preferably the first portion comprises first and second parts, the second part extending through an active region of the device and having a narrower width than the first part. A method of forming and filling the via is also disclosed.