Abstract: An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.

Abstract: Disclosed are systems and methods which provide a busy tone or signal for use in communication collision avoidance in a wireless network, such as a WLAN, a cellular network, or other point-to-multipoint wireless network. An intelligent busy tone generator, upon the proper conditions, transmits a busy tone or signal to one or more wireless device which may otherwise be hidden from particular communications. According to embodiments the busy tone mimics a carrier sequence of an actual transmission to facilitate the wireless devices recognizing the channel as busy. Because the original uplink packet may be interfered by transmission of a busy tone carrier-sense sequence, embodiments are provided with interference cancellation capability. Interference cancellation circuitry of embodiments may operate in a plurality of modes, including a training mode (including an online training mode, an offline training mode, and a hybrid or combined mode) and an operating mode.

Abstract: The invention is used in video coding. Systems, apparatuses and methods for processing an order-16 integer transform from an order-8 transform are provided. The order-16 transform method involves expanding an order-8 transform by generating an order-16 integer matrix and a scaling matrix.

Abstract: A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

Abstract: A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.

Abstract: The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.

Abstract: An antenna system comprising a ground plane structure on a substrate, an antenna space on the substrate adjacent to the ground plane structure, the antenna space including an ungrounded antenna therein with an associated first resonant length, an extension of the ground plane projecting into the antenna space, the ground plane extension defining a second resonant length that includes at least part of its own length and at least part of a length of the ground plane structure.

Abstract: A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.

Abstract: An LCD display apparatus arranged to display image on an image display surface at an image frame rate of M image frames per second, the apparatus including a backlight arrangement comprising an LED backlight device for providing backlight illumination to said image display surface and a backlight controller for controlling the generation of backlight and intensity distribution of backlight illumination on said image display surface; wherein the backlight controller comprises a processor configured to generate a set of backlight illumination data with reference to the intensity distribution characteristics of the image content of said image frame according to a predetermined relationship, wherein said set of backlight illumination data contains information on the required intensity distribution of backlight on said image display surface for said image frame; and to generate a plurality of backlight illumination frames for each said image frame during the duration of said image frame based on said set of backli

Abstract: A transmitting and receiving system including an antenna element having first and second current paths, and a meander feed line connected to said first and second current paths, the meander feed line including a radiating portion parallel to the first current path, wherein a current in the radiating portion is in a direction opposite of a current in the first current path, and wherein a current in the second current path is in a direction the same as the current in said radiating portion.

Abstract: Systems and methods for employing switched phase shifters and a feed network to provide a low cost multiple beam antenna system for wireless communications. The present systems and methods may also facilitate multi-band communications and employ multi-diversity. The present systems and methods allow communication systems to achieve enhanced performance for communication or other services such as location tracking. The present systems and methods may employ switched phase shifters, multiple diversity antennas and/or a feed network having a multi-layer construction to provide an antenna system with low losses, low external component count and/or which is thin and compact.

Abstract: A debinarizer and a hardware-based method for debinarizing a binary bit stream into symbols comprising predefined binary sequences are disclosed in which predefined binary sequences and their corresponding symbols are represented as tree structures. A binary sequence is debinarized by traversing one of the tree structures to determine a corresponding symbol. Similar tree structures may be combined to form a single tree structure. The tree structures may be implemented as a finite state machine.

Abstract: A server for streaming media includes a functional module operable to perform the following functions within a Real Time Streaming Protocol (RTSP) session: receiving a command that requests a list of available streaming presentation options; and generating and transmitting the requested list over a network connection.

Abstract: Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

Abstract: A method for use in video compression is disclosed. In particular, the claimed invention relates to a method of more efficient fractional-pixel interpolation in two steps by a fixed filter (240) and an adaptive filter (250) for fractional-pixel motion compensation.

Abstract: A stacked multi-chip package with an EMI shielded component has first and second substrates mounted together by a grid array of metallic connecting nodes, such as a solder Ball Grid Array. Each substrate has a conductive plane associated with it. An electronic component is mounted between the first and second substrates and is surrounded by a group of the metallic connecting nodes that are also electrically connected to the conductive planes of both substrates to form a conductive Faraday cage about the component.

Abstract: A method of determining the location information of a plurality of wheels mounted on a vehicle by obtaining a relationship between the lateral location of a wheel and the polarity of a transverse acceleration transmitted by an accelerometer of a wheel in response to a lateral turn of the vehicle in a direction of a lateral side of the vehicle and determining the lateral location of a wheel with reference to the polarity of the transverse acceleration signal transmitted by the accelerometer of the wheel upon the vehicle undergoing a lateral turn.

Abstract: A light guiding strip and a double-sided planar light apparatus are provided. According to one embodiment of the present invention, the double-sided planar light apparatus includes a plurality of light guiding strips, wherein the plurality of light guiding strips are positioned in a planar arrangement, each of the plurality of light guiding strips including a first plurality of light emitting surfaces disposed toward a first direction and a second plurality of light emitting surfaces disposed toward a second direction, each of the plurality of light guiding strips further including a first end and a second end configured to receive light, wherein the plurality of light guiding strips emit light from the first and second plurality of light emitting surfaces. Reflectors and light diffusion patterns on the light guiding strips provide control and independence over the two sides of the planar light apparatus.

Abstract: A method for performing link adaptation in a Multiple Input Multiple Output (MIMO) system comprises: receiving a signal at a receiving unit of the MIMO system, calculating channel state information (CSI) from the received signal, and calculating a plurality of values of a parameter from the CSI, the parameter mapping to an error rate of the system, the mapping being substantially one-to-one within a range of interest of the error rate, each one of the calculated values corresponding to one of a plurality of Modulation Coding Schemes (MCSs).

Abstract: The present invention provides a backlight assembly and a display system having the same, characterized in that the backlight assembly comprises: a plurality of light emission units and a control unit. Each unit having M kinds of emission components, each of the M kinds of emission components emitting light of a spectrum which is different from each other, wherein M is a positive integer equal to or greater than two. The control unit receives a first signal and determines a second signal according to the color information of the first signal, and individually controls light emission of each emission component of the plurality of light emission units based on the second signal, wherein the light emissions from the plurality of light emission units generate a spatially-dependent spectrum distribution, and the light emission of each light emission unit forms a color gamut in a color space which is individually different from others.