Abstract: System and method for constructing and customizing icons for use in a graphical user interface (GUI) is disclosed. A GUI is provided with a set of available user interface components that may be selected and combined by a user to create new icons or to modify existing icons. Each icon comprises a plurality of components and each component may be represented by a set of primitives, or component objects. With respect to each component, a user may select an object from the set of objects to represent the component and the selected objects are combined to create a coherent icon used for representing applications, functions and documents in an operating system or applications program. The combination of the component objects is performed based on sets of rules associated with the individual components, which rules dictate the positioning, scaling, graphical combination and available coloring of the component.

Abstract: A battery charging system is disclosed that includes an efficient switch mode power supply, multiple linear current limiters, and feedback means to allow the switch mode power supply to operate at the minimum voltage necessary to operate a power load and charge batteries. Furthermore, the switch mode power supply is capable of producing the maximum power required by the system, such as when the battery charger is used in conjunction with operation of a electronic device with peak load demands such as when a hard disk is accessed in a portable computer. Two control mechanisms are found in the battery charging system. The first mechanism is an input used to control the switch mode power supply output voltage from an external source. In one embodiment, this is done by referencing a first voltage to that internal to the switch mode power supply. The second mechanism is to limit the current within the switch mode power supply not controlled by an external source.

Abstract: A battery charger is disclosed for recharging reusable batteries in a manner that prevents overcharging of the same. The charger includes a voltage source and non-dissipative shunt arrangement that can be customized to charge any number of batteries. The charger may be a current limiting power supply that is controlled by the voltage or charge state of the batteries being recharged. The non-dissipative shunt includes a pair of transistors for each pair of batteries and an inductor placed one end between the battery pair and another end between the transistor pair. An oscillator, having two phases of equal, but opposite phase, is used to control each transistor to apply charge to a given battery during one phase and then to allow the charge to equalize between the battery pair during the second phase. The equalization is continued until both batteries reach a full charge without overcharging any one battery.

Abstract: A subgroup object displayed by a drawing program in a window area as part of a more complex display can be edited by creating a new drawing area or "window" called a "zoom" window and reproducing the subgroup in the new drawing window. Within the zoom window, the subgroup object is effectively broken into its component objects, and the component objects can be individually manipulated using standard techniques. More particularly, the subgroup object is copied into the new window by copying the list of individual objects which comprise the subgroup object into the main group object list associated with the new window. As each individual object is redrawn in the new window, it is scaled and translated so that it appears in the same relative position in the new window as it did in the original window, but at a position and size relative to the new window.

Abstract: A system for controlling initialization and self test operations in a multiprocessor system facilitates the use of central processing units based around differing microprocessor types. More specifically, the present invention involves storing configuration information, initialization self-test code, and boot code specific to each processor, memory module, or I/O circuit board in non-executable form in a non-volatile memory, on the respective circuit board, and storing the executable portion of the boot code needed by the initial boot processor in a centrally accessible non-volatile memory.

Abstract: Standard protocols, such as those commonly used on LAN networks, are used to connect nodes to an enterprise network via a wide area wireless network. Within the appropriate protocol stacks, the standard protocols are optimized by filtering some packets, eliminating and reducing the size of other fields and substituting still other fields to reduce the size of the data packets. The optimized data packets can be transmitted over the wireless WAN increasing WAN efficiency. The optimization is accomplished by inserting an additional optimization layer into the protocol stack between the existing layers. The optimization layer accepts the normal protocol signals generated by the surrounding layers amid generates outputs which mimic protocol layers which the surrounding layers expect. Consequently, the optimization layer operates transparently with respect to the existing protocol stack layers.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: An application management system for achieving a common user access (CUA) interface throughout multiple applications of a computer system is described. The system includes an operating environment having an application control module (ACM) that is run-time bound and executable by the applications. The ACM furnishes generalized procedural codes for each application. The application uses data structures to define the appearance and operation of the application to the ACM. The system also integrates the application program interfaces (API's) of an operating environment graphic user interface (GUI) system and a database management system (DBMS) within the ACM. The invention reduces the programming required for applications and improves consistency in programming across multiple applications.

Abstract: Data is written to a memory subsystem in a computer system, wherein the data is supplied by an input/output (I/O) bus. The I/O bus provides a STROBE signal, the occurrence of which is indicative of a time when an I/O data word on the I/O bus is valid. A first I/O data word provided by the I/O bus, after a first occurrence of the STROBE signal, is stored in a data buffer. A memory data word is retrieved from the memory subsystem in response to the first occurrence of the STROBE signal. A second I/O data word provided by the I/O bus, after a second occurrence of the STROBE signal, is stored in the data buffer. The memory data word is modified by the first and second I/O data words to form a modified data word. Error detection information corresponding to the modified data word is generated and the modified data word and the error detection information are written to the memory subsystem.

Abstract: An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS.sub.-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.

Abstract: An apparatus and method for recovering power dissipated by a semiconductor integrated circuit includes a thermoelectric generator which converts the heat generated by the integrated circuit into electrical energy. The electrical energy is used to drive a fan or other airflow generating device to cause heated air to be moved away from the integrated circuit and cooler air to be drawn to the integrated circuit to absorb further heat from the integrated circuit. In the described embodiment, the thermoelectric generator is a Peltier cooler positioned between the integrated circuit and a heatsink. The Peltier cooler is operated in the Seebeck mode to generate power in response to the temperature differential between the integrated circuit and the heatsink.

Abstract: An improved omni-directional non-occluding solder pad design for printed circuit boards comprising a plurality of spokes radiating outward from a through-hole on the printed circuit board, with a ring concentric to the through-hole that intersects each of the plurality of spokes at approximately a perpendicular angle. The ringed-spoke configuration eliminates the need to ensure proper orientation of the solder pad on the printed circuit board prior to a wave soldering process since the symmetrical ringed-spoke design is omni-directional. The concentric ring structure provides an additional contact area of solder between the printed circuit board and a computer chassis. This additional contact area of solder ensures that there is a sufficient electrical connection between the printed circuit board and the computer chassis such that when the printed circuit board is mounted to the computer chassis, a proper grounding connection is provided.

Abstract: A power conversion method and apparatus convert an AC input voltage signal or a DC input voltage signal to a DC output voltage signal suitable for driving a DC load. The power converter includes a first voltage stage coupled to a first pair of input terminals to receive a rectified AC input voltage signal. A second voltage stage is coupled to a second pair of input terminals to receive a DC input voltage signal from a battery source. A transistor drive circuit is connected between the input terminals and the first and second voltage stages. The drive circuit causes energy to be stored in either the first or second voltage stage depending upon whether an AC or a DC voltage signal is applied to the input terminals. The stored energy is released to a third voltage stage to produce a DC output voltage at output terminals coupled to a power supply of a portable device, such as a personal computer.

Abstract: A system controller controls subsystems in a computer. The system controller is operable with a processor in a computer. The system controller includes a plurality of decoders, each of the decoders being operable with a different processor type and being selectively activated so that the system controller can operate with a plurality of processor types. The decoders, when activated, receive processor request signals from the processor and decode the processor request signals to provide subsystem controller request signals. A controller receives the subsystem controller request signals and controls the subsystems based on the subsystem controller request signals.

Abstract: A method and apparatus for downloading instructions and other information to a peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system which downloads instructions from the ISA compatible computer to an random access memory (RAM) accessible by the peripheral controller. The peripheral controller then executes these instructions to emulate the functions of conventional INTEL 8042 and 8742 series integrated circuits. The peripheral controller also provides other features not provided by the conventional 8042 or 8742 by executing other downloaded instructions located in the RAM.

Abstract: A portable data entry unit capable of being set up for right handed or left handed operation. The lower housing of a casement for the data entry unit is provided with four carrier mount receiving regions configured to secure a strap bracket. Two strap carrier mounts are used, one each in an appropriately located region for either handed configuration. The rear external surface of the lower housing has a central recessed portion flanked by two support portions. Each support portion is provided with a co-molded surface region to enhance the gripability of the unit.

Abstract: An improved bus architecture system for use in a multi-processor computer system has a shared address bus and a shared data bus, and has at least two separate memory modules. The system reduces the bus latency time by allowing sequential address requests to different memory modules to begin before previous cycles are terminated. Preferably, the physical memory is mapped onto several separate memory modules which will increase the probability that concurrent address requests from different processors on the common bus are for different memory modules. The processor address determines which memory module contains the data for a new request. If the memory module addressed by the new request differs from the memory module addressed by the current request, the bus controller may issue an early address request for the new data. While the early address request for the new request is being processed, the current bus cycle for the data located in the first memory module is completed on the shared data bus.

Abstract: A multi-use notebook computer carrying case includes a top cover member and a bottom cover member. An accordion-like shroud connects the sides of the top and bottom cover members. A bottom tray having a height adjust mechanism is secured within the bottom cover member. The bottom cover member houses a plurality of drawers capable of being extended away from the bottom cover member to expose a storage compartment and provide additional working surface area. The bottom cover member further includes a height adjustable wrist pad. A protective windshield housed within the top cover member, is selectively engageable to protect against a hostile environment.