Abstract: The disclosed computer-implemented method can include (i) receiving a plurality of submissions from respective virtual functions requesting at least some resources from a hardware accelerator, (ii) scheduling, by a scheduler, divisions of the resources to the respective virtual functions based on a total actual execution time slice of each respective virtual function, and (iii) allocating the divisions of the resources to the respective virtual functions according to the scheduling. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

Abstract: A processor for implementing a last use cache policy is configured to access data in a portion of a cache, determine that the data in the portion of the cache is no longer needed, and mark the data in the portion of the cache as non-dirty responsive to the determining that the data in the portion of the cache is no longer needed. The marking of the data as non-dirty is indicative that the data in the portion of the cache is not to be evicted from the cache to a memory.

Abstract: A system comprises a machine check architecture and a processor. The machine check architecture is configured to log hardware errors. The processor is configured to obtain a log of one or more of the hardware errors from the machine check architecture and/or to generate a copy of the log. The processor is further configured to either (1) deliver the log to an in-band agent and the copy of the log to an out-of-band agent or (2) deliver the copy of the log to the in-band agent and the log to the out-of-band agent. Various other devices, systems, and methods are also disclosed.

Abstract: A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.

Abstract: Temporary system adjustment for component overclocking is described. In accordance with the described techniques, a processor and/or memory are operated according to first settings. During operation of the processor and/or the memory according to the first settings, a signal triggers a temporary adjustment of operation of the processor and/or the memory according to second settings. Responsive to the request, operation of the processor and/or the memory is switched to the second settings without rebooting. After a duration, operation of the processor and/or the memory is switched back to the first settings. In one or more implementations, at least one of the first settings or the second settings overclock the processor and/or the memory.

Abstract: In response to a video aspect ratio of a frame of video not matching an aspect ratio of a display panel of a display device, a source device of a processing system transmits only the frame to the display device and metadata indicating that the display device is to generate bars for letterboxing or pillarboxing. By generating the bars for letterboxing or pillarboxing at the display device instead of transmitting the bars from the source device to the display device or storing the bars at a frame buffer of the display device, the processing system conserves power and bandwidth.

Abstract: Systems and methods are provided related to a scheduler to receive a job request from a virtual function associated with a tenant for execution by at least one processing unit. The scheduler validates the job request in accordance with one or more defined restrictions associated with the tenant and, responsive to successful validation, provides the job request for execution by the processing unit via one or more physical functions associated with the processing unit. In certain embodiments, multi-level enforcement of the defined restrictions are provided via user-mode and kernel-mode drivers associated with the virtual function that are also enabled to validate job requests based on the defined restrictions.

Abstract: A technique includes determining a base decision rate; monitoring for key events; and based on the base decision rate and the monitoring, determining a time at which to generate an action to be performed by an application entity of an application. The base decision rate includes a baseline rate at which the application is directed to determine new actions to be performed by the application entity. In some examples, the base decision rate is determined using a trained AI model, by applying information about the state of the application to the model and obtaining the base decision rate in response. In some examples, key events are unexpected events that occur in the application. In some examples, since the base decision rate represents a rate at which to generate actions, given the current state of the application, the key events, which represent unexpected events, override or modify the base decision rate.

Abstract: A technique for rendering is provided. The technique includes mapping a randomization portion of an item of identifying information to a random block of an address space; mapping a linear portion of the item of identifying information to an element within the block; and accessing the element.

Abstract: Devices and methods for allocating components of a safety critical system are provided. The processing device comprises resources including memory, a host processor and a plurality of processors connected to the resources via a shared pathway of a network and configured to execute an application based on instructions from the host processor. Each of the plurality of processors is assigned to one of a plurality of criticality domain levels and isolated pathways are created, via the shared pathway, between the plurality of processors and the plurality of resources based on which of the processors are assigned to one or more of the plurality of criticality domain levels to access one or more of the plurality of resources. The application is executed using the network. The isolated pathways are, for example, created by disabling one or more switches. Alternatively, the isolated pathways are created via programmable logic.

Abstract: Scheduling and clock management for real-time system quality of service (QoS) is disclosed. In an implementations, a resource manager determines a target work rate based on respective job deadlines of a plurality of jobs on a processing platform. Determining the target work rate can include ordering the plurality of jobs based on the respective deadlines, determining an amount of work required to reach each of the respective deadlines, identifying one deadline among the respective deadlines as a most constraining deadline based on the amount of work required to reach that one deadline, and determining the target work rate based on the most constraining deadline. The resource manager adjusts a clock rate of the processing platform based on at least the target work rate.

Abstract: A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.

Abstract: The disclosed computer-implemented method includes transforming, from a time domain into a frequency domain, a sound signal into a transformed sound signal. The transformed sound signal has a phase component and a magnitude component. The method also includes filtering the phase component of the transformed sound signal by applying a quantized mask from a machine-learning model to the phase component, and generating a filtered sound signal by transforming, from the frequency domain into the time domain, the transformed sound signal comprising the magnitude component and the filtered phase component. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems, apparatuses, and methods for implementing gradient adaptive ringing control for image resampling are disclosed. A blending alpha calculation circuit generates a blending alpha value for a set of input pixels based on a normalized gradient calculated for the set of input pixels. The normalized gradient is a low-pass filtered gradient of the set of input pixels divided by a maximum gradient for the set of input pixels. The normalized gradient is passed through a mapping function so as to generate the blending alpha value. The mapping function is pre-tuned based on filter coefficients, video content type, pixel format, and so on. An interpolated pixel is generated for the set of input pixels by blending ringing free and ringing prone interpolation coefficients, or by blending results between ringing free and ringing prone interpolation filters, with the blending weight for each filter based on the blending alpha value.

Abstract: A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.

Abstract: An apparatus translates transaction requests using a bus protocol translation lookup table (LUT) that comprises bus protocol translation data. A bus protocol translation controller generates the outgoing translated transaction request by translating the incoming transaction request using the bus protocol translation data from the bus protocol translation LUT. The controller translates a received response from the target unit to a response in a first bus protocol for a corresponding requesting unit. Associated methods are also presented. In some examples, the bus protocol translation data corresponds to each of a plurality of requesting units for translating between an incoming transaction request sent via a first bus protocol to an outgoing translated transaction request sent via a second bus protocol for the at least one target unit.

Abstract: Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

Abstract: The disclosed device can include a bitcell array located on a first metal layer including a first subarray of bitcells and a second subarray of bitcells; a first write driver device coupled to the first subarray of bitcells from a first end of the first subarray; a second write driver device coupled to the second subarray of bitcells from a first end of the second subarray; a third write driver device coupled to the first subarray of bitcells from a second end of the first subarray; and a fourth write driver device coupled to the second subarray of bitcells from the second end of the second subarray. Various other devices, systems, and methods of manufacture are also disclosed.