Abstract: A technique for rendering is provided. The technique includes performing a visibility operation to generate shade space visibility information and reconstruction information; performing a shade space shading operation based on the shade space visibility information generate shaded shade space textures; and performing a reconstruction operation based on the reconstruction information and the shaded shade space textures.

Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.

Abstract: Systems, apparatuses, and methods for achieving higher cache hit rates for machine learning models are disclosed. When a processor executes a given layer of a machine learning model, the processor generates and stores activation data in a cache subsystem a forward or reverse manner. Typically, the entirety of the activation data does not fit in the cache subsystem. The processor records the order in which activation data is generated for the given layer. Next, when the processor initiates execution of a subsequent layer of the machine learning model, the processor processes the previous layer's activation data in a reverse order from how the activation data was generated. In this way, the processor alternates how the layers of the machine learning model process data by either starting from the front end or starting from the back end of the array.

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for performing video operations is provided. The technique includes characterizing a frame as a flash frame; setting the flash frame as a non-intra frame; prohibiting encoding of frames other than the flash frame with reference to the flash frame; and applying a positive quantization parameter (“QP”) offset to the flash frame.

Abstract: Graphics processing unit (GPU) selection based on a utilized power source, including: determining that an apparatus is using a direct current (DC) power source instead of an Alternating Current (AC) power source; and causing, in response to the apparatus using the DC power source, the apparatus to preferentially utilize an integrated graphics processing unit (iGPU) over a discrete graphics processing unit (dGPU) while using the DC power source.

Abstract: The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An exemplary method for dynamically changing frequencies of clocks for the data link layer without downtime involves switching a first queue on a first end of a data link and a second queue on a second end of the data link from a pacing mode to an asynchronous mode. The exemplary method also involves modifying a frequency of a clock associated with the data link. The exemplary method further involves returning the first queue and the second queue from the asynchronous mode to the pacing mode upon modifying the frequency of the clock. Various other devices, systems, and methods are also disclosed.

Abstract: Embodiments herein describe identifying voltage potentials in separate cells that can be combined so that a dummy gate between or in the cells can be removed. For example, some combinational logic cells such as XOR gates, XNOR gates, and half-adders are formed from coupling two combinational cells in sequence. Typically, a dummy gate is placed between those cells since they have different voltage potentials. However, if the cells have the same voltage potentials, then the dummy gate can be removed and the cells can overlap by sharing a net. This can reduce the overall size of the cell.

Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a first insulating layer overlying a substrate, forming a second trench capacitor within a second insulating layer overlying the first insulating layer, and connecting the first and second trench capacitors through connection vias that extend through the second insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more such layers.

Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more tiers of trench capacitors.

Abstract: In order to efficiently process graphics data, operations are performed including allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.

Abstract: Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.

Abstract: An electronic device includes a memory and a processor. The processor acquires a platform management profile, the platform management profile including information defining one or more platform management policies. The processor provides the platform management profile to platform management drivers executing on one or more electronic devices, the platform management profile being configured so that each of the platform management drivers can extract the one or more platform management policies from the platform management profile and use the one or more platform management policies for controlling operating states of elements (e.g., functional blocks, devices, etc.) of the respective electronic device.

Abstract: A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.

Abstract: A system, apparatus, and method for electronically transferring value using a portable electronic device. In one embodiment, a method for transferring funds to or from play a portable electronic device to facilitate playing a game of chance on a portable electronic device.

Abstract: Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.

Abstract: A secure data recorder provides targeted collection and storage of working data from any subsystem of a computing device. The data recorder gathers and stores device working data based on stored configuration data. The configuration data indicates memory and storage locations on the device from which to gather working data and storage locations at which the data recorder stores the gathered working data. The data recorder operates in a secure execution environment during all of the pre-boot stage of the computing device. The data recorder further allows a user to update the Basic Input/Output System (BIOS) of the computing device based on a firmware image that may be received via the network. The data recorder also facilitates gathering of working data, over time, that may reveal a malfunction of particular hardware configurations and particular software configurations.