Abstract: A method and apparatus for processing program instructions, utilizes native fixed length instructions that include at least one flag modification enable bit. The flag modification enable bit is typically sent with the operation code and other information in the native instruction and is set to allow updating of one or more flags, such as stored in flag registers, associated with non-native instructions, such as variable length instructions. In addition, a flag modification enable bit may be set to preserve flag bit setting for variable length instructions that are emulated using the fixed length native instructions, to prevent overwriting of flag settings during emulation of variable length instructions.

Abstract: A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.

Abstract: A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by the operation pipeline include blending operations for fragment blocks received from a graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. Other operations include selective reads and writes to the memory array, clearing functions, and swapping functions. Mask values included in the commands executed to control the operation pipeline allow for selectivity with respect to portions of the data packets, or blocks, to which the operations are applied.

Abstract: A method and apparatus determines if a BLT command meets BLT override criteria. If the BLT override criteria is met, the method and apparatus performs a BLT command override and instead executes a FLIP operation instead of performing a BLT operation.

Abstract: A method and apparatus for virtual address translation include processing that begins by receiving a memory access request that includes a virtual address. The processing continues by determining whether a physical address translation has been performed for the virtual address. Note that a physical address translation translates the virtual address into an address. The address either corresponds to physical address of memory or is further translated into another physical address of memory. The processing continues when the address, which resulted from the physical address translation or the another physical address translation, is stored in a translation look aside table (TLB). When the physical address translation or the another physical address translation has not been performed, the processing retrieves a physical page address based on a portion of the virtual address.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Abstract: A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.

Abstract: A method and apparatus for supporting anti-aliasing oversampling in a video graphics system that utilizes a custom memory for storage of the frame buffer is presented. The custom memory includes a memory array that stores the frame buffer as well as a data path that performs at least a portion of the blending operations associated with pixel fragments generated by a graphics processor. The fragments produced by a graphics processor are oversampled fragments such that each fragment may include a plurality of samples. If the sample set for a particular pixel location can be compressed, the compressed sample set is stored within the frame buffer of the custom memory circuit. However, if such compression is not possible, pointer information is stored within the frame buffer on the custom memory, and a sample memory controller included on the graphics processor maintains a complete sample set for the pixel location within a sample memory.

Abstract: A method for controlling two monitors on the basis of an input-side pixel data stream, in which one part of each line of the input-side pixel data stream is displayed on one of the monitors and another part of the line is displayed on another of the monitors, comprises the storing of one part of the line of the input-side pixel data stream in one FIFO memory device and the storing of the other part of the line of the input-side pixel data stream in another FIFO memory device. The readout of one FIFO memory device takes place with the pixel frequency with which one monitor is operated while the readout of the other FIFO memory device takes place with the pixel frequency with which the other monitor is operated. Thus, a moderately priced and high speed monitor control circuit is realized.

Abstract: During a fast forward search of a multimedia presentation, the audio portion of the multimedia presentation is pitch-adjusted and played back in order to assist the user in determining where within the multimedia presentation the playback currently is located. In another embodiment, the audio playback portion of the multimedia presentation can be buffered such that only intermittent portions of the audio are played back in such a manner that is audible to an end user in determining where in the multimedia presentation the playback routine is located. Another embodiment accommodates a multimedia presentation being reversed will have its audio portion buffered and played back in forward in order to assist the user in determining where in the multimedia presentation the rewind currently is. In addition, an individual word detect can be performed during the rewind whereby each word is individually detected and played forward after its detection.

Abstract: In accordance with the present invention, a write behind controller receives control information from a display device controller in order to determine a current location available in a frame buffer for receiving information. Write accesses of the frame buffer by a rendering engine are prohibited if the access is to an area below a currently available location of the frame buffer. Generally, the rendering engine will be stalled when the requested address location has not yet displayed its data. Subsequently, the write access to the frame buffer is allowed when location has been rastered.

Abstract: A video overlay switching apparatus and method utilizes a common video scaler that receives input video data. A programmable switching mechanism, such as a register-controlled multiplexer, receives video information from the video scaler, either scaled video or unscaled video, and selectively routes the video data to any one of a plurality of video overlay generators to facilitate selective display of overlay data on a specified display device. The programmable switching mechanism also facilitates programming of frame buffer space for each display engine, based on which video overlay generator has been selected to receive input video.

Abstract: A method and apparatus for successive linear approximation to obtain a specific point on a non-linear monotonic function include processing that begins by obtaining a T-coordinate for the specific point. The specific point includes a T-coordinate and an N-coordinate. The process then continues by selecting a minimum point and a maximum point on the non-linear monotonic function to bound the specific point. The processing then continues by deriving a linear reference between the minimum and maximum points. The process then proceeds by obtaining a reference N-coordinate that lies on the linear reference based on the T-coordinate. The process then continues by determining a reference T-coordinate lying on the non-linear monotonic function based on the referenced N-coordinate. The process then continues by determining whether the referenced T-coordinate is substantially similar to the T-coordinate.

Abstract: A power consumption reduction circuit and method utilizes a memory clock source and a memory clock divider circuit that generates divided memory clock output signals as a plurality of corresponding independent clock signals to a number of different processing engines. A memory clock divider circuit and method selectively activates a plurality of independent clock signals in response to received condition data. In one embodiment, an engine clock source is also coupled through a switching circuit such that it is selectively output to one or more processing engines. The switching circuit disables the output from the engine clock based on register condition data. In another embodiment, a plurality of memory read latch circuits are controlled by a memory read latch control circuit. The memory read latch control circuit is operative to dynamically activate and deactivate the plurality of memory read latches based on detected memory read requests to facilitate memory access activity-based power reduction.

Abstract: A circuit and method serves as a slave interface to support both register read/write and monitor detection operations by a graphics controller chip, or other display data source, with a plurality of display devices. The circuit supports differing monitor detection protocols including, for example, I2C protocol and non-DDC type protocols. The circuit may be set in two modes, a register mode and a bypass mode. The register mode is used to facilitate standard I2C protocol to a display device. Display detection bypass circuitry is used to selectively bypass the register based display detector interface by connecting input pins to any two of a plurality of I/O pins so that the system may be used for monitor detection of a plurality of different display devices, such as CRTs and LCDs to facilitate multiprotocol display detection.

Abstract: A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal.

Abstract: In accordance with a specific implementation of the present invention, the control portion of a graphics processor receives a command having both a data portion and a data duration portion. When the data duration portion indicates the data is transient data for short-term use, the control portion stores the data associated with the data portion at the first memory partition. When the data duration portion indicates the data is persistent data for long-term use, the control portion stores the data associated with the data portion at a second memory partition. In a multiple processor system, transient data may be stored only in a memory partition associated with a first processor, while persistent data may be stored in multiple memory partitions, one for each graphics processor.

Abstract: A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the delayed output signal and producing an error signal. Each of the delay elements includes a first input associated with a negative output and a second input associated with a positive output, whereby the positive and negative outputs are selectively coupled to a constant voltage source responsive to a first bias voltage and to a ground. The positive and negative outputs are responsive to a second bias voltage and the first and second voltage inputs. The constant voltage source and the positive output are coupled via a first transistor and the constant voltage source and negative output are coupled via being a second transistor.

Abstract: In accordance with one embodiment of the present invention, the client maintains a count of the number of commands issued to a circular buffer associated with the drawing engine. For every predetermined number of commands issued, a store command is issued that includes the current count. The current count when executed is stored in a location generally associated with the graphics engine. The client periodically reads the current count from the storage location and compares this value to its current count. The result of this comparison provides an estimated value of the number of commands which have not been executed by the graphics engine. When the estimated value exceeds a predetermined value the client will delay issuing further commands, until subsequent current count values stored in the location indicate that the number of commands stored in the command buffer has fallen below a predetermined value.