Abstract: A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

Abstract: A method and apparatus for transposing bits include processing that begins by receiving a multiple bit input. The multiple bit input may be received from memory for executing a read operation from a processing device or for a write operation to memory. The processing continues by determining whether a transposed bit function is enabled. When the transposed bit function is enabled, a set of tri-state transposed drivers are enabled to couple out bit lines to the multiple bit input in a transposed fashion. In addition, a set of tri-state non-transposed drivers are disabled such that they are not coupled to the output bit lines. When the transposed bit function is not enabled, the non-transposed drivers are enabled and the tri-state transposed drivers are disabled such that the multiple bit input, when coupled to the output bit lines, is not transposed.

Abstract: In accordance with a first mode of operation of the present invention, a portrait image is received from a system device. The portrait image is translated and stored within the graphics engine memory such that it can be displayed on a landscape monitor that has been rotated 90 degrees. Likewise, when portrait data stored within the memory is sent to the system it is translated such that it is sent back in the same format received by the system. In a second mode of operation in accordance with the present invention, a landscape image received by the graphics adapter is stored in the graphics adapter memory without any translation.

Abstract: A method and apparatus for compressing image data for storage in a memory device is presented. This is accomplished by separating the image data into a plurality of pixel sets where each pixel set is of a predetermined pixel set size. A discrete cosine transform is then performed on each of the pixel sets to produce a plurality of transform coefficients. These transform coefficients are then compressed to produce a compressed data set. Compressing the transform coefficients preferably includes determining a coefficient set that includes a portion of the transform coefficients that reasonably approximate the pixel set. These coefficients are then mapped to known ranges such that a limited number of bits can encode values throughout these predetermined ranges. The mapped coefficients resulting from the mapping step are then manipulated to fit within a limited number of bits assigned to each coefficient. The limited number of bits is determined partially based on the coefficient set to be compressed.

Abstract: A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.

Abstract: A method and apparatus utilizes a display engine scaler to access source image that is located in memory, such as a frame buffer and also controls a second scaler, such as a front end scaler of a 2D/3D engine, which also accesses the frame buffer and is capable of scaling from a frame buffer memory and storing the scaled image back to the frame buffer.

Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Abstract: A graphic interface device produces a video signal for a display such that the user may select between landscape and portrait image display modes. The graphic interface device has a pixel data memory array from which a video output signal is derived. A primary graphics engine renders graphics in a landscape orientation in conjunction with a frame buffer. The primary landscape graphics engine stores rendered graphics to the pixel data memory array and also copies selected graphics in data blocks within the frame buffer called surfaces. In order to provide other display modes to display images in different physical orientations, a mode control is provided in conjunction with a rotated pixel data array buffer to facilitate the rendering of portrait oriented graphics by the primary landscape graphics engine. In addition, to facilitate the efficiency and speed of rendering portrait oriented graphics, a secondary portrait graphics engine is provided.

Abstract: A graphic accelerator interface device for a computer is provided. The accelerator has a host data path that includes a plurality of comparators, each assigned to permit os/application access to a different “surface” which is defined by an address range corresponding to a block of data in a frame buffer. Unlike the prior art, an access flag register is associated with the host data path such that each surface assigned to a comparator has associated read and write flags. Whenever a read or a write occurs to one of the assigned surfaces via the host data path, the corresponding flag is set. Preferably, for os/application access, the surfaces contain data in an untiled format which the graphic accelerator uses in a tiled format. The invention affords more efficient, i.e.

Abstract: A specific embodiment of the present invention discloses a method and apparatus for processing a digitized signal. Specifically, a digitized signal is received at a Lifting Scheme filter at a first data rate. The Lifting Scheme filter provides a representation of the digitized signal at a second rate. The Lifting Scheme filter can be implemented as a fully pipelined filter, or a recursively called filter.

Abstract: A software test system and method detects a hardware configuration of each of plurality of test stations that are coupled to a processor such as a test center server. The software test system and method stores hardware configuration data representing the detected hardware configuration of each of the plurality of test stations and provides the hardware configuration data for use in determining which of the plurality of test stations is a suitable test station for testing target software to be tested. The test stations are dynamically configurable to contain and operate differing operating systems, test software, software to be tested and other suitable applications. A plurality of test stations coupled to a test center server each have different hardware configurations.

Abstract: A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality of flags each correspond to a class of instruction occurring in the instruction pipeline circuitry. Pipeline control circuitry cooperates with the instruction pipeline circuitry, as part of the basic execution cycle of the computer, to maintain the value of the flags to record failures of an attempt to execute in the first mode two mode instructions of the corresponding respective instruction classes, to be triggered by a timer expiry to switch the value of the flags, thereby to switch the instruction pipeline circuitry from one of the processing modes to the other for the corresponding instruction class.

Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.

Abstract: A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.

Abstract: An advanced dot-stretch anti-sparkle technique analyzes the stream of display pixels to determine an optimal time for performing the dot-stretch operation. The system searches the stream of display pixels for a current and previous pixel that are the same color. The system then performs the host access and the dot-stretch during the pixel match. If a pixel match is not detected within a predetermined period of time, the search for two matching pixels is abandoned and the dot-stretch process is implemented.

Abstract: A video graphics system employs a method and apparatus for improving throughput of the system. The video graphics system includes a graphics driver, a graphics processor, and a memory. Responsive to receiving a drawing command from an application, the graphics driver determines whether the graphics processor can begin executing the drawing command within a desired period of time. When the graphics processor is heavily loaded and cannot begin executing the command within the desired period of time, the graphics driver partially processes stored vertex information associated with the drawing command, and preferably stores the pre-processed vertex information in the memory. The graphics driver then preferably issues a new drawing command relating to the stored pre-processed information and instructing the graphics processor not to perform any of the processing already performed by the graphics driver. The graphics driver is preferably implemented in software and stored on a computer-readable storage medium.

Abstract: A method and apparatus for loading data from memory to a cache is provided. The method and apparatus provide substantially improved performance, especially in conjunction with large data arrays for which each element of data is processed completely at once and need not be later accessed. A technique is provided to allow a data element to be loaded directly to a cache location corresponding to the local variable used to process that data element, thereby avoiding copying of the data element to multiple cache locations. In conjunction with the use of non-caching stores of processed results back into main memory, this technique completely avoids cache thrashing within the framework of a conventional microprocessor architecture. This technique is ideally suited for high-performance processing of streaming multimedia data including video processing.

Abstract: A method and system controls multiple TV tuners to allow a user to watch live video at high quality based on a video capture level independent of a video capture quality used to record playback video. The method and system provides an independent TV tuner from which to capture video that will be replayed wherein the capture quality of the video from the tuner will be independent from the quality other tuner. Accordingly, an delayed video stream can have a lower capture quality setting without affecting the capture quality of primary video being viewed by a user.

Abstract: A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events.

Abstract: An apparatus marks files within a content archive. The content archive contains a database that has a plurality of content files. The content archive also contains a plurality of entries or records. Each of the entries corresponds to a distinct one of the plurality of content files. Each of the entries also includes a played field that is automatically set when the corresponding content file has been played. The content archive also includes a writing module that is configured to record a new content file to the content archive and, if insufficient space is available, to overwrite a content file for which the played fields are set. According to one aspect, the plurality of entries also includes an entry corresponding to an overwritten content file previously contained within the database that is no longer contained within the database. The database may contain references to content no longer in the database.