Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.

Abstract: A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.

Abstract: A method and system connects a display device or other device to a computer system during operation of the system. Initially a run time EDID (Extended Display Identification Data) flag is set to a first value indicating no run time EDID is required. By monitoring for an interrupt a checking is carried out for a change to a new display device in the computer system. If no change to a new display device is detected, the run time EDID flag is checked. If the run time EDID flag indicates that no run time EDID is required, an EDID is read from a video BIOS on a graphics adapter in the computer system. If the run time EDID flag indicates that a run time EDID is required, an EDID is read from a video memory on a graphics adapter in the computer system. If a change to a new display device is detected, the run time EDID flag is set to a second value and EDID is then downloaded from the new display device.

Abstract: A method and apparatus for indexing and locating key frames in streaming frame data and variable-frame-length data is described. Fast and efficient location of desired key frames in both directions (e.g., forward/backward, future/past) is provided. An estimate of the distance to the desired key frame is made and a seek performed according to that distance. At the location specified by the seek, key frame seek assist data are obtained. The desired key frame is located or a new seek is performed, depending on the key frame seek assist data obtained. By placing the key frame seek assist data at readily identifiable locations, efficient location of key frames is provided. The key frame seek assist data may be tailored to optimize efficiency for seeking in a particular direction, for example, backwards. The seek process is correspondingly configured to favor seeking in the more efficient direction.

Abstract: An address generator provides for generation of addresses for a plurality of different tests by allowing for primitive polynomial-based pseudo-random bit-streams to be shifted into the address generator. Embodiments of the present invention utilize the address values to generate data values to be stored in a memory under test. Likewise, an expected data value is generated and compared to the stored value. A data comparator verifies the stored data to the expected value. A single latch stores compare results for a plurality of memory locations.

Abstract: A method and apparatus for optimizing production yield and operational performance of integrated circuits is provided. A nominal operating voltage is used to categorize integrated circuits into a plurality of performance categories, and the nominal operating voltage is adjusted for each performance category to optimize the yield within that performance category. Integrated circuits may be operated at different operating rates according to their performance categories. The operating rates of an integrated circuit may be controlled by programming a clock register for the integrated circuit. Correct programming of the clock register may be assured by programming a one-time-programmable device. A one-time-programmable device may also be used to program the nominal operating voltage once the optimal nominal operating voltage has been determined. A diagnostic program may be used to select optimum performance parameters for an integrated circuit.

Abstract: A method and apparatus for detecting copy protection included in an input video signal is described. Two types of copy protection are particularly addressed, including techniques that imbed copy protection pulses and copy protection phase flips in the video signal. A method for preserving copy protection is also presented, where the input video signal is first examined to determine if copy protection has been included in the input video signal. The input video signal then converted to component video data, which removes any copy protection present. An output video signal is then generated from the component video data, and when it was determined that the input video signal includes copy protection, the copy protection is recreated in the output video signal.

Abstract: The television system for displaying images on a television display has a source of a series of video fields. An active de-interlacer receives first field data from a first field of the series of video fields and second field data from a second field of the series of video fields, and produces de-interlaced data and control data. A format converter has a vertical scaler then directly receives the de-interlaced data and produces vertically scaled data therefrom. The format converter also has a re-interlacer that receives the vertically scaled data and the control data, and produces a re-interlaced frame. A horizontal scaler is connected to receive the re-interlaced frame and to produce therefrom a horizontally scaled re-interlaced frame. Display drivers receive the horizontally scaled re-interlaced fame and produce therefrom television display signals for forming images on a television, a high definition television of other type of television display.

Abstract: A method and apparatus for parallel processing of geometric aspects of video graphics data include processing that begins by determining whether an object-element is within a clipped volume. The processing continues by determining whether the object-element is to be clipped when it is within the clipped volume. The processing then continues by performing in parallel, a clipping function and an attribute derivation function upon the object-element when the object-element is to be clipped. The attribute derivation function may include performing a light function, texture map function, etc.

Abstract: An improved deinterlacing technique reconstructs regions of an image that change monotonically in the vertical direction (i.e., vertical deinterlacing). The present invention adapts to the image content without using spatio-temporal interpolation techniques. Rather, deinterlacing in accordance with the teachings of the present invention uses, for example, four localized input pixel values to produce an output pixel value that minimizes spatial artifacts (i.e., accurately reconstructs regions that change monotonically in the vertical direction). In another embodiment, an overlay scaler shares overlay scaling circuitry and deinterlacing circuitry to provide a cost effective implementation of a unique deinterlacing circuit. In another embodiment, a plurality of offsets are used in addition to three or more pixels.

Abstract: A method and apparatus includes processing for restricting at least one video output of a computing system based on copy protection information. Such processing begins by receiving a video signal and associated copy protection information (e.g., Macrovision). The processing continues by interpreting the copy protection information. When the copy protection information indicates copy restriction, the processing continues by altering at least one video output. The video output may be altered by disabling a monitor output, adjusting a refresh rate to be incompatible with a television refresh rate, altering an image of the video signal, and/or inserting a message in a non-current interlaced field of the video signal.

Abstract: A method and apparatus for supporting multiple bus masters on an AGP bus is presented. A first bus master is configured as an AGP bus master and utilizes the AGP request portion of the AGP bus structure to issue bus master requests. A second bus master is configured as a PCI bus master and utilizes the PCI bus master request portion of the AGP bus to assert bus master requests. When bus master grants are received via the AGP bus, status lines are used to determine the character of the bus master grant. When the status lines indicate that the bus master grant is an AGP bus master grant, the AGP bus master performs AGP bus master operations. When the status lines indicate that the bus master grant is a PCI bus master grant, the PCI bus master is enabled and allowed to perform PCI bus mastering operations.

Abstract: A method and apparatus for eliminating memory contention in a computation module is presented. The method includes, for a current operation being performed by a computation engine of the computation model, processing that begins by identifying one of a plurality of threads for which the current operation is being performed. The plurality of threads constitutes an application (e.g., geometric primitive applications, video graphic applications, drawing applications, etc.). The processing continues by identifying an operation code from a set of operation codes corresponding to the one of the plurality of threads. As such, the thread that has been identified for the current operation, one of its operation codes is being identified for the current operation. The processing then continues by determining a particular location of a particular one of a plurality of data flow memory devices based on the particular thread and the particular operation code for storing the result of the current operation.

Abstract: A method and apparatus for determining a byte select vector for a crossbar shifter include processing that begins by storing data in a first set of byte locations and in a second set of byte locations. Typically, a data operand is written into the first and a shift value is written into the second set of byte locations. The processing continues by obtaining a shift amount value for the data. The processing then continues by determining, for each byte multiplexor of a set of byte multiplexors associated with a corresponding output byte, whether a wrapped condition will occur based on the shift amount for the data. When the wrap condition occurs, a wrap shift amount is determined based on a mode of shifting. The processing then continues by generating a byte select vector for the set of byte multiplexors based on the wrap shift amount and the shift amount.

Abstract: A method and apparatus for improving performance of an AGP device is provided. In one embodiment of the invention, a second-level cache is provided for a TLB, and part of the data or part of the address that is not otherwise used for determining a TLB entry is divided by a prime number to determine which TLB entry to allocate. One embodiment of the invention provides the ability to load multiple cache lines during a single memory access without incurring additional transfer, storage, or management complexities. The full number of bits of each memory access may be used to load cache lines. One embodiment of the invention loads multiple cache lines for translations of consecutive ranges of addresses. Since the translations included in the multiple cache lines cover consecutive ranges of addresses, the relationship between the multiple cache lines loaded for a single memory access is understood, and additional complexity for cache management is avoided.

Abstract: In a specific embodiment, a system for providing video includes a system bus, which in one embodiment is an Advanced Graphics Port (AGP) busy. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Abstract: The method provides for sort independent alpha blending of fragments of a graphic image. A sequence of fragments has opaque fragments and transparent fragments. The opaque fragments are rendered to a frame buffer having at least a z buffer, the z buffer having stored therein z values of front most opaque fragments. Transparent fragments are stored in a list in a transparent fragment buffer. The transparent fragments are sequentially read from the list and are discarded if they are occluded by an opaque fragment. When not occluded, the transparent fragments are stored in a list. The z buffer is cleared and the transparent fragments are read sequentially from the list. Z values are stored in the z buffer for back most transparent fragments. The transparent fragments are again sequentially read from the list. Z values of currently read transparent fragments are compared to z values in the z buffer of corresponding fragments.

Abstract: An object to be displayed on a display screen is converted into at least one graphic primitive having associated texture data. The texture data is analyzed to determine whether operations associated with the texture data are commutative. A processor or a display engine is selected for performing the texture data operations based on in part the analysis.

Abstract: An integrated circuit receiver includes a differential input receiver having a plurality of differential input transistors. A variable well voltage supply circuit varies the well voltages of the differential input transistors to change the input transistors threshold voltages to provide hysteresis control by varying well voltages of input transistors in opposite directions. A method for reducing noise for an integrated circuit receiver includes receiving an input signal by a differential input receiver, and changing into opposite directions the input transistors threshold voltages to provide hysteresis control by varying the first and second well voltages associated with each of a first differential input transistor and a second differential input transistor. At least one feedback signal is used from the differential input receiver as input to the variable well voltage supply circuit to vary the first and second well voltages to facilitate hysteresis control of the differential input receiver.

Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.