Abstract: The present invention provides a scheme for compressing the color components of image data. The pixel data is grouped into a plurality of tiles for storage. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table is provided that includes a flag that can be set for each tile that is compressed. In a data transfer from memory to a graphics processor, the tile table is examined to identify those tiles that are compressed and must be decompressed prior to use. In one embodiment, a number of compression schemes are available for use on a tile and the best compression scheme is chosen on a tile by tile basis. The invention includes an identifying code for each compression scheme (stored as a value in each compressed tile).

Abstract: A trellis decoder decodes a stream of encoded symbols, including symbols of a first type (e.g. symbols encoded with a first trellis code) and symbols of a second type (e.g. encoded with a second, more robust, trellis code), without storing path indicators along a trellis for symbols of the first type. In this way, limited memory may be used to store path indicators along the trellis for symbols of the second type. This allows for more accurate decoding of the symbols of the second type. For transitions from symbols of the second type to symbols of the first type, states of the trellis decoder may be stored. In this way, paths may be traced back along the trellis for trellis decoding, without the path indicators for the symbols of the first type.

Abstract: The system for updating a clock in an electronic device, such as a personal computer, has a receiver system having an input for receiving a real time signal and having an output on which is provided digital information representative of the real time signal. An extraction module is operatively coupled to the receiver system, the extraction module extracting at least a current time value from the display data. An update module is operatively coupled to the extraction module, the update module updating the clock in the computer when the current time value of the digital information differs from a current value of the clock in the computer. In one embodiment a validating unit is operatively coupled between the extraction module and the update module. The validating unit compares channel identification data derived from the display data to time zone data in the computer, the time zone data being indicative of a time zone in which the computer is currently located.

Abstract: A system and method for handling errors is provided. Errors related to the processing and storage of inverse discrete cosine transform (IDCT) image data cause hardware to become stalled. Stalled hardware may result in multiple image frames being dropped or lost during video playback. To avoid the stalling of hardware, the hardware is used to analyze the data being processed. Data being stored may be analyzed to determine if any error-characteristics, such as overflow or underflow, are present in the storing of the data. The data is manipulated to avoid stalling due to the error-characteristics.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant is analyzed. As reduced activity is identified, power conservation modes are implemented. In a normal mode of operation, a clock signal generated through an external oscillator is provided to a phase locked loop (PLL). An output clock signal from the PLL is then provided to several dividers to generate system clock signals. In a reduced mode of operation, the output clock from the external oscillator is provided to a divider, bypassing the PLL. Video processing components then use clock signals based on the external oscillator. In a suspend mode, both the PLL and the external oscillator are disabled.

Abstract: A program information player automatically skips over any intermediate channel changes as a result of interrupting a prior recording of a selected program. The program information player includes a program sequence playback information generator. The program sequence playback information generator analyzes selected program identifier information and recorded program history log information and, in response, generates program sequence playback information without user intervention. The program sequence playback information includes a sequence of time stamp information associated with the selected program identifier information. According to one embodiment, the program sequence playback information directs memory to play back the selected program corresponding to the selected program identifier information by, for example, skipping over any intermediate channel changes. For example, the program sequence playback information may represent a read pointer in memory during playback.

Abstract: A system and methods are provided for presenting processed audio data and processed video data to corresponding outputs in a synchronized manner. Video and audio data from a multimedia stream are received by a processing system. The video data is processed through a video processor. The audio data is processed through an audio processor. Processed audio data is stored in memory through a VIP data port. A bus-master engine is used to delay a transfer of the audio data from memory to an output port. The delay is determined so as to allow video data enough time to be processed and output in synchronous with the audio data transferred from memory. Once the delay has been overcome, the bus-master asserts a trigger in the data bus to initiate the transfer from memory to the output port.

Abstract: A system and methods are shown for performing a hardware performance analysis of graphics hardware and an application program. An application program generates a set of function calls. The function calls are translated to a native command set. The native command set is stored within a database. Software simulations and hardware emulations are used to compare the stored native command set data to a hardware architectural description of the graphics hardware. Data collected from the simulations are used to provide a performance model from which the performance of a graphics hardware executing commands for the application program can be determined.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A method and apparatus for reducing instruction dependencies in extended SSA form instructions includes examining a first instruction of a worklist, wherein the worklist contains instructions in the extended SSA form that have a source, a previous link and a write mask and further produce an output. The method and apparatus further includes examining at least one second instruction of the worklist, wherein at least one second instruction is a source of the first instruction. Lastly, the method and apparatus includes translating the plurality of instructions in the worklist into a second plurality of instructions in the extended SSA form where the second plurality of instructions contains less instruction dependencies such as previous links.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system based on display content. Display content is monitored to determine whether the display content is changing. New display content is compared to old display content to determine if the display content is changing. If the display content has not changed, a frame rate used to output display data is reduced. A color depth associated with the display data is also reduced. Power consumption can be reduced when it is determined that display content is not changing.

Abstract: A method and apparatus for interpolating pixel parameters based on the plurality of vertex values includes operating first and a setup mode and a calculation mode. The method and apparatus includes, while in a setup mode, generating a plurality of differential geometric values based on the plurality of vertex values, wherein the differential geometric values are independent of a parameter slope between the plurality of vertex values. While in a calculation mode, a first geometric value and second geometric value are determined based on a pixel value, a plurality of vertex values and the differential geometric values. A pixel value is determined for each of the plurality of pixels based on the vertex parameter value, the first geometric value and the second geometric value. Thereupon, pixel parameters may be interpolated on a per-pixel basis reusing the differential geometric values.

Abstract: A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.

Abstract: A TV signal reception system is configured to include adjustable components and a controller to provide instructions to adjust the adjustable components. By pre-arranging configurations corresponding to multiple variants of world wide TV standards, the TV signal reception system may avoid the hardware costs of accomplishing the reception of multiple standards of with parallel hardware for each standard and/or variant.

Abstract: A method and apparatus for providing rendering of subsections of screen space receives render commands associated with different screen subsections, such as from a command buffer populated by a coprocessor, and determines which screen section is currently being rendered by a rendering engine, or stated another way, which screen section the host processor wishes to have rendered, and evaluates screen subsection data that is associated with a received rendering command. The screen subsection data identifies a screen subsection for which the command refers. The method includes executing the command if it is determined that the command refers to a current screen section being rendered.

Abstract: In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

Abstract: Systems and methods are provided for supporting an external display on a portable device. A system on a chip (SOC) of the portable device provides a first set of graphics data to a graphics controller. The embedded graphics controller renders the first set of graphics data for output using an LCD screen integrated with the portable device. The SOC renders a second set of graphics data and provides rendered graphics data to an external display interface. The external display interface formats the rendered graphics data for output on an external, remote display.

Abstract: A stacked die configuration for use in an IC package includes a first IC die mechanically coupled to a substrate material. Mechanically coupled to the first IC die is an interposer having an aperture adapted to receive a second IC die. Mechanically coupled to the first IC die and fitting within the aperture of the interposer is a second IC die. As a result, both the overall height of the IC package and the length of the bond wires connecting each of the members of the stacked die configuration may be reduced.

Abstract: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.