Abstract: A cross-coupled, latching voltage level converter to convert a signal from a first voltage domain to a second voltage domain and hold an output logic level is disclosed. The converter includes back-to-back first and second inverter circuits coupled to a first voltage source operable at a first voltage level. A transistor is coupled between an output of the first inverter and ground potential, the first transistor having a gate coupled to an input signal operable at a second voltage level. A second transistor is coupled between the output of the second inverter and ground potential, the second transistor having a gate coupled to an inverse of the input signal operable at the second voltage, wherein a terminal of the second transistor delivers an output signal operable at the first voltage level and corresponding to the same logic state as the input signal.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A block-based image compression method and encoder/decoder circuit compress a plurality of pixels in a block where each pixel includes a corresponding color value and a corresponding luminance value. The encoder circuit includes a luminance-level-based representative color generator to generate representative color values for each of a plurality of luminance levels to produce at least a high color value and a low color value. In response to generating the representative color values, the luminance-level-based representative color generator associates each of the pixels in the block with one of the plurality of representative color values to produce corresponding bitmap values. The encoder circuit further includes a color type block generator to perform at least one of: (a) generate block color data indicating a regular/alternate color block type and (b) representing a block color type by ordering the representative color values that are to be sent to a decoder.

Abstract: A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters.

Abstract: Apparatus and methods are disclosed for controlling the memory controller and, in particular, controlling signaling of the memory controller to a memory via memory interface during a static screen condition. An apparatus includes static image detection logic that is configured to detect when image data being displayed by a display controller is static and to communication detection of static image data to the display controller. The apparatus also includes control logic within the display controller responsive to the static image detection logic, where the control logic is configured to detect a level of a line buffer within the display controller and to send a signal to a memory controller directing the memory controller to issue a signal to a memory to enter a self-refresh mode, thereby turning off at least one memory clocking circuit within the memory controller. A corresponding method is also disclosed.

Abstract: A digital pixel clock generation circuit receives image data and corresponding image presentation time information from at least one external image source. The digital pixel clock generation circuit includes an image presentation timing error determination circuit that produces desired pixel clock frequency control information, such as pixel output clock adjustment control information, based on a difference between an expected presentation time and an actual presentation image time information. A programmable digital waveform generation circuit is programmed based on the produced desired pixel clock frequency and has an input that is responsive to an independent clock source, that is independent from the clock source of the external image source. The programmable digital waveform generation circuit provides a digital representation of an independently generated desired pixel clock which is then output to a digital to analog converter (DAC).

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: Methods and apparatus for matching voltages between two or more circuits within an integrated circuit is disclosed. The apparatus includes a comparator circuit, comparing supply voltages to first and second circuits. The comparator outputs a variable error voltage based on the comparison, the error voltage related to the difference in voltages. The error voltage is supplied to a variable current control circuit that variably sinks one of the supply voltages to a common potential in order to increase the IR drop in the circuit supplying voltage to one of the first and second circuits, thereby affording voltage adjustment in order to match the first and second circuits. A corresponding method is also disclosed.

Abstract: A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew.

Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract: A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages.

Abstract: A system and method is provided for synchronizing the presentation of audio data with video data. Audio transport packets are received through a demultiplexer from a multimedia transport stream. A transport stream synchronization manager is used to lock a system time clock, local to the demultiplexer, to a program clock reference provided through the multimedia transport stream. Presentation time stamps are provided with the audio transport packets to indicate when decoded audio data is to be output. A packetized elementary stream synchronization manager maintains synchronization by adding or dropping audio packets from the audio transport packets. If the packetized elementary stream manager is unable to acquire synchronization it must defer synchronization back to the transport stream synchronization manager. Otherwise, processed audio packets are passed to an elementary stream synchronization manager that attempts to synchronize the delivery of audio data through a sample rate conversion of the audio data.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: An input output ring for a semiconductor device is disclosed that uses power buffers having widths that vary from the widths of the input and output buffers. In one embodiment, the pitches between bond pads are the same, in another embodiment the pitches between the bond pads can vary. In another embodiment, the number of bond pads is greater than the number of associated active buffer areas. By connecting two power bond pads to a common buffer the inductance associated with the buffer is reduced, thereby reducing the number of active buffers needed to be dedicated to providing power to the semiconductor device.

Abstract: A method and apparatus for parallel processing of pixel information within a video graphics circuit is accomplished when the video graphics circuit includes a set-up engine, an edgewalker circuit, a span processing circuit, and a plurality of pixel processing circuits. In such an embodiment, the set-up engine receives vertex information and produces object-element information therefrom. The object-element information is provided to the edgewalker circuit, which in turn produces span definition information. The span definition information identifies the starting pixel of a span and the starting pixel parameters. The span information is received by the processing circuit and converted into a plurality of pixel parameters. The plurality of pixel parameters are provided to the plurality of pixel processing circuits wherein each of the plurality of pixel processing circuits processes corresponding pixel parameters to produce pixel information in accordance with the information provided by the processing circuit.

Abstract: A device and method are provided that generate an early warning disconnect signal from an electrical connector supplying external power to a connected device. The connected device includes an early warning disconnect power management circuit, operational to generate power consumption control information in response to generation of the early warning disconnect signal from the electrical connector. In one example, the electrical connector includes a lock release mechanism and a signaling mechanism, the signaling mechanism is operationally coupled with the lock release mechanism and configured to generate the early warning disconnect signal from the electrical connector to the connected device prior to the lock release mechanism being in an unlocked state.

Abstract: An AGC circuit includes both wide-band and narrow-band VGAs. Two power monitors monitor the power level of the two VGAs. Based upon the signals provided by the power monitors, the AGC circuit derives two error terms. The AGC circuit filters and combines the error terms to determine a desired adjustment to the total gain and a desired adjustment to the distribution of the gain between the wide-band VGA and the narrow-band VGA. The AGC circuit also minimizes the noise figure of the narrow-band VGA subject to linearity constraints.

Abstract: A digital filter pre-calculates C(1)*S(n?1), C(2)*S(n?2) . . . C(p?1)*S(n?p+1), prior to the arrival of sample S(n). As such y ? ( n ) = ? k = 0 k = p - 1 ? C ? ( k ) * S ? ( n - k ) may be calculated as a result of a single further multiply and accumulate operation, upon arrival of the symbol S(n). This, significantly reduces the latency of the filter.

Abstract: A block-based image compression method and encoder/decoder circuit compresses a plurality of pixels having corresponding original color values and luminance values in a block according to different modes of operation. The encoding circuit includes a luminance-level-based representative color generator to generate representative color values for each of a plurality of luminance levels derived from the corresponding luminance levels to produce at least a block color offset value and a quantization value. According to mode zero, each of the pixels in the block is associated with one of the plurality of generated representative color values to generate error map values and a mode zero color error value. According to mode one, representative color values for each of at least three luminance levels are also generated to produce at least three representative color values, corresponding bitmap values and a mode one color error value.