Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

Abstract: A video expansion card makes electrical contact with a mating connector via a mixed signal card edge connector formed on a first edge of the video expansion card. The mixed signal card edge connector includes a plurality of contacts to make electrical contact with the mating connector. The plurality of contacts carries, for example, any combination of two channel audio-in and two channel audio-out signals, two S-video signals, two television signals and two composite video signals, or any other suitable signals. The video expansion card may be coupled to an expansion card bracket in a housing having an aperture adapted to receive the mixed signal card edge connector. The housing may be, for example, a personal computer system chassis or cabinet, a processor-based device or any suitable device. A motherboard card edge connector is formed on a second edge of the video expansion card, and couples the video expansion card to the housing.

Abstract: An equalizer for use in a communication receiver includes an infinite impulse response (IIR) feedback filter operated in acquisition and tracking feedback modes on a sample by sample basis to form a hybrid Decision Feedback Equalizer (DFE) architecture. In acquisition mode, soft decision samples from the filtered received signal are input to the IIR filter. In the tracking mode, hard decision samples from a slicer are input to the IIR filter. Acquisition and tracking operating modes are selected in accordance with a set of decision rules on a sample by sample basis based on the quality of the current hard decision. If the current hard decision is low quality, then the soft decision sample (acquisition mode) is used. If the current hard decision is high quality, then the hard decision sample (tracking mode) is used. In such manner, the DFE is operated in a hybrid mode, i.e., using both soft and hard decisions on a sample by sample basis.

Abstract: A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

Abstract: A method of determining when cable modems in a distributed digital data delivery service over cable TV hybrid fiber coaxial cable network have a headroom problem and resolving said problem. The method involves measuring the burst power from each cable modem, and if the burst power is too low, requesting the cable modem whose burst power is too low to increase its transmit power, and keeping track of which modems have been requested to increase their power. If a predetermined number of requests to increase power have not resulted in the cable modem transmitting with sufficient power for reliable reception, the cable modem is listed as having a headroom problem. Subsequent requests for upstream bandwidth from all modems with headroom problems are analyzed to determine if the requested burst size is too large and will result in a headroom problem. If so, a calculation as to the maximum number of spreading codes that each modem with a headroom problem can simultaneously transmit on without a headroom problem.

Abstract: A method for rendering pixels for display includes generating stencil values on a per pixel basis for storage in stencil buffer memory; selecting a group of stencil values that represent a block of pixels; generating compressed stencil data associated with the group of stencil values; and performing stencil testing on a corresponding incoming block of pixels using the compressed stencil data.

Abstract: A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.

Abstract: Graphics processing circuitry includes processing circuitry operative to generate pixel information in response to primitive information, and a correction circuit, coupled to the processing circuitry, operative to generate gamma corrected pixel information in response to the pixel information. The correction circuit converts the floating point pixel information generated by the processing circuitry into a gamma corrected fixed-point value so that gamma space pixel data is stored in the frame buffer. This fixed point gamma corrected pixel information, converted from the floating point pixel information, compensates for the non-linear display characteristics exhibited by current display devices. This results in the display output being more accurate; thereby, improving the appearance quality of the resulting image.

Abstract: A variable clock control information generator receives vertical blank interval information corresponding to a vertical blank interval (VBI) during display rasterization. The vertical blank interval is a period of time in a video display signal that temporarily suspends transmission of video data as is known during display rasterization, to allow a display to return back up to (retrace) the first line of the display after scanning the end of the display. In response to the received vertical blank interval information, the variable clock control information generator produces memory clock control information to change the frequency of a memory clock divider signal during the detected vertical blank interval.

Abstract: Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

Abstract: A system and methods are provided for processing graphics to be displayed in a portable device. A current mode of operation of the portable device is identified. In a normal mode of operation, image data associated with the portable device is rendered by a graphics system of the portable device and stored in memory external to the graphics system prior to display. When a screen refresh mode of operation is identified, image data rendered by the graphics system is compressed and stored in memory integrated internal to the graphics system. The present disclosure has the advantage of allowing the memory external to the graphics system to be disabled during the screen refresh mode of operation, reducing power consumed by the portable device.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.

Abstract: A method and apparatus for the display of a viewing events list, wherein a viewing events list includes receiving a plurality of viewing event indicators, wherein each of the plurality of viewing event indicators is associated with event information. The viewing event indicators includes some form of indication of a corresponding underlying viewing event. The method and apparatus further includes prioritizing the viewing event indicators based on the viewing event information and at least one priority rule. The method and apparatus further includes generating the viewing events list including a priority-based listing of the viewing event indicators. Through the association of the priority rules and the corresponding available viewing event indicators, a structured list is provided prioritizing viewing events to assist in a viewer selecting what to watch based on define preferences and priority rules.

Abstract: A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.

Abstract: A technique for approximating output values of a function based on LaGrange polynomials is provided. Factorization of a LaGrange polynomial results in a simplified representation of the LaGrange polynomial. With this simplified representation, an output value of a function may be determined based on an input value that includes an input mantissa and an input exponent. Based on a first portion of the input mantissa, a point value and at least one slope value are provided. Each of the at least one slope value is based on a LaGrange polynomial approximation of the function. Thereafter, the point value and the at least one slope value are combined with a second portion of the input mantissa to provide an output mantissa. Based on this technique, a single set of relatively simple hardware elements may be used to implement a variety of functions with high precision.

Abstract: Method of providing closed captioned data to a television viewer comprised of detecting closed captioned data signals transmitted in conjunction with a television signal, decoding the data signals to caption display signals, and displaying the caption display signals on an auxiliary screen separate from a screen displaying the television signals.