Abstract: A system and method for applying non-homogeneous properties to multiple video processing units (VPUs) in a multiple VPU system are described. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different VPUs in the system is combined, or merged, or composited to produce a frame to be displayed. In load balancing modes, each VPU in the system performs different tasks as part of rendering a same frame, and therefore typically executes different commands. In various embodiments, efficiency of the system is enhanced by forming a single command buffer for execution by all of the VPUs in the system even though each VPU may have a different set of commands to execute in the command buffer.

Abstract: A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.

Abstract: A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

Abstract: A video receiver for SCART input includes an input configured to receive a composite video signal, RGB signals, and a switch-indicating signal, a first digitizer module coupled to the input and including a one-bit slicer configured to receive and convert the switch-indicating signal to a one-bit digital signal, the first digitizer further including a downconverter configured to convert the one-bit signal to a multi-bit digital signal with non-abrupt transitions between a logical zero and a logical one, and a combiner module configured to receive and combine indicia of the composite video signal and the RGB signals to produce a total video output signal as a function of the indicia of the multi-bit digital signal.

Abstract: Methods and apparatus for translating messages in a computing system are disclosed. In particular, a disclosed method for converting messages in a computer system includes receiving a command message from a processing unit where the message is defined according to a transport protocol that utilizes command messages using an address to communicate commands to devices in the computer system. The command message is translated to an interface standard by mapping the address into an address field of a packet constructed according to the interface standard. Corresponding apparatus that perform the methods are also disclosed.

Abstract: Apparatus and methods are disclosed for controlling the memory controller and, in particular, controlling signaling of the memory controller to a memory via memory interface during a static screen condition. An apparatus includes static image detection logic that is configured to detect when image data being displayed by a display controller is static and to communication detection of static image data to the display controller. The apparatus also includes control logic within the display controller responsive to the static image detection logic, where the control logic is configured to detect a level of a line buffer within the display controller and to send a signal to a memory controller directing the memory controller to issue a signal to a memory to enter a self-refresh mode, thereby turning off at least one memory clocking circuit within the memory controller. A corresponding method is also disclosed.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: An apparatus, for use in a receiver configured to receive electronic signals, for identifying digital signals that are available for reception, includes a timing recovery device configured to receive an incoming signal, related to a transmitted signal, the incoming signal having a first symbol rate, and to re-sample the incoming signal to provide a second symbol rate, and an analyzer that is in communication with the timing recovery device and that is configured to make a determination as to whether a difference between the second symbol rate and a third symbol rate of a transmitter providing the transmitted signal is within an acceptable tolerance and to use the determination in an analysis of whether the transmitted signal is available for reception.

Abstract: A method and system are provided for aligning signals in a communication system. The method and system include alignment logic or functionality configured to compensate for signal propagation discrepancies when communicating signals between one or more other devices. The alignment logic may operate to adjust one or more communicated signals, so that signals that may have different propagation times arrive at one or more devices at a desired time. The system and method may be used when initializing a communication system and before communicating data. The system and method operate to adjust one or more signals, such as a data strobe signal in a memory system for example, so that the one or more signals arrive at one or more devices spaced apart in time within a defined tolerance at a desired time. The alignment logic is used to compensate for signal propagation delays which can be associated with a signal propagation path.

Abstract: Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request in a second protocol responsive to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the memory write request in the generated memory write request in the second protocol to produce a translated memory write request. The method may also include receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

Abstract: Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed by an interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, all interrupts received by the interrupt handler are formed into an event message according to a uniform format regardless of the manner in which the interrupt is signaled. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Event messages are stored in an event buffer for access and handling by the host. The event buffer is managed by the interrupt handler.

Abstract: A method of signal processing according to an embodiment includes estimating a response of a transmission channel during a symbol period. Based on an estimated response of the transmission channel, components of a model of a phase noise process during the symbol period are estimated. Based on the phase noise process model, an estimate of a symbol received during the symbol period is obtained.

Abstract: Systems, methods, and apparatus for noise reduction include noise estimation from blanking interval information. Such systems, methods, and apparatus may also include temporal filtering, scene change detection, inverse telecine, and/or DC preservation.

Abstract: A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics aperture relocation table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. Thus, unique addresses need not be generated for each VPU.

Abstract: The present disclosure relates to methods and apparatus for controlling power consumption of a plug-in card or circuit module. The disclosed method, in particular, controls power to a circuit module and includes implementing a user interface and power manager to automatically control the power state of the circuit module by, among other things, powering the module up or down using a simulated hot unplug of the device. The apparatus further includes use of an I/O interconnect to allow the system BIOS to simulate the hot unplugging of the module.

Abstract: A graphics processing circuit includes an anti-aliasing and stippling circuit operative to provide a primitive texture coordinate set in response to vertex data, the anti-aliasing and stippling circuit performing anti-aliasing operations, in parallel, with at least one appearance attribute determination operation on the vertex data, a rasterizer, coupled to the anti-aliasing and stippling circuit, operative to generate a pixel texture coordinate set in response to the primitive texture coordinate set, and apply an appearance value to a pixel defined by the pixel texture coordinate set, and a texture circuit, coupled to the rasterizer, operative to retrieve the appearance value from a corresponding one of a plurality of textures in a multi-texture map in response to the pixel texture coordinate set, the multi-texture map including data representing point, line and polygon texture data.