Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: An audio/video separator provides a high-performance and cost-effective solution to analog TV reception with only one A/D converter and a minimum of analog IF components. The apparatus may operate on a digitized TV signal and, when integrated with a digital video processor, process video signals while separating audio signals. The resultant audio and video signals may be considered to have excellent signal quality due to highly optimized demodulation architecture and digital signal processing techniques on both audio and video data paths.

Abstract: In accordance with a specific aspect of the present disclosure, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized and written to an output buffer location.

Abstract: A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fixed, relatively small page size. The page table is broken into fragments made up of pages that are contiguous in physical address space and logical address space and have similar attributes. Fragments in logical address space begin on known boundaries such that the boundary indicates both a starting address of a fragment and the size of the fragment. Corresponding fragments in physical address space can begin anywhere, thus making the process transparent to physical memory. A fragment field in a page table entry conveys both fragment size and boundary information.

Abstract: To detect at least one of a copy protection indicator and a redistribution control indicator in an analog video signal, the video format of the analog video signal is determined, e.g., by detecting the horizontal frequency and vertical frequency of the signal. Based at least on the determined video format, a region of the analog video signal that may contain the indicator is identified. The region may for example be one or more video lines in a vertical blanking interval. The region is examined until the indicator is detected. The indicator is confirmed, e.g., by re-detecting one or more occurrences of the same indicator value(s) later in the video signal. Once confirmed, the indicated copy protection and/or redistribution control may be effected by limiting either or both of copying and redistribution of the analog video signal. The indicator may for example be Copy Generation Management System Analog plus Redistribution Control (CGMS-A+RC) information.

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

Abstract: The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30, 2004 and entitled SIMD PROCESSOR AND ADDRESSING METHOD.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calculated tag distance is used to determine whether the pixels are outside a local image area defined about the uncached pixels. Pixels determined to be outside the local image area are replaced with the uncached pixels. The motion prediction cache can be organized as sets of cache lines and the method can be performed for each of the cache lines in one of the sets. The definition of the sets can be changed in response to cache performance. Similarly, the local image area can be redefined in response to cache performance.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: A TV signal reception system is configured to include adjustable components and a controller to provide instructions to adjust the adjustable components. By pre-arranging configurations corresponding to multiple variants of world wide TV standards, the TV signal reception system may avoid the hardware costs of accomplishing the reception of multiple standards of with parallel hardware for each standard and/or variant.

Abstract: Systems and methods for dynamic power management of electronic devices are disclosed. In one form, a system employing dynamic power management for electronic devices includes a central processing unit operable to process information via a communication bus. The system includes a clock generator and a voltage generator coupled to the processing unit and operably associated with the communication bus having multiple operating voltage levels. The clock generator and communication bus are operated at variable clock rates and voltage levels to ensure bandwidth requirements are satisfied for communicating and processing information. In this manner, power consumption of the system may be dynamically managed while providing sufficient bandwidth for the system.

Abstract: A variable reference voltage circuit controllable in closed loop, for calibrating off-chip and on-chip drivers, margining and optimizing a reference voltage, for interfaces such as DDR2 or any other suitable interface. In one example, the on-chip variable reference voltage circuit, coupled to external fixed reference voltage, includes control logic and an array of switchable resistor elements (pull-up and pull-down resistors) that may each be selectively switched in or out of the circuit to change the reference voltage being supplied to an on-chip receiver.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: The invention described herein includes a system, method, and computer program product for adding functionality to an application program. The invention includes a tool which can be used in conjunction with any of a plurality of application programs. The tool can be represented to a user by a tool icon on a desktop. After creating or opening a file or other object with an application program, the user can drag and drop a tool icon representing the tool into the application window. This allows the tool program to operate on the object. A windowing system event handler receives information from a user interface regarding the dragging and dropping of the tool icon. The fact that the tool icon has been dragged and dropped into the application window is reported by the windowing system event handler to a base module. The base module mediates communication between the tool program and the application program.

Abstract: To operate a computer, a first graphical user interface of a server application is displayed in a first display region, which has user interface elements for presenting output from the server application and receiving runtime user input to the server application. A second display region is also provided, in which graphical user interfaces are provided. The second display region has a defined location and may be a sidebar. In response to user interaction with the first graphical user interface, a first user interface element is selected from the first graphical user interface. The first user interface element presents a type of output from the server application or receiving a type of input to the server application. Further, a client application is configured to display a second graphical user interface in the second display region, such that the second graphical user interface includes a second user interface element corresponding to the first user interface element.