Patents Assigned to ATI Technologies ULC
  • Efficient processing of translucent objects in video keying
    Patent number: 11039153
    Abstract: A video keying processing device is provided which comprises memory configured to store data and a processor configured to determine, which pixel portions, in a YUV color space of a first video comprising a foreground object and a background color, represent the foreground object and the background color of the first video. The processor is also configured to, for each pixel portion of the first video determined to represent the foreground object and the background color, convert YUV values of the pixel portion to red-green-blue (RGB) color component value and determine a blended display value for each RGB color component of the pixel portion based on a blending factor. The processor is also configured to generate a composite video for display using the blended display values of each pixel portion determined to represent the foreground object and the background color.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 15, 2021
    Assignee: ATI Technologies ULC
    Inventors: Yubao Zheng, Gabor Sines
  • Pixelation optimized delta color compression
    Patent number: 11037357
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 15, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Graphics processing architecture employing a unified shader
    Patent number: 11023996
    Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 1, 2021
    Assignee: ATI Technologies ULC
    Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
  • Method and apparatus for asynchronous scheduling
    Patent number: 11023242
    Abstract: A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 1, 2021
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Greg Sadowski, Syed Zohaib M. Gilani
  • Encoder with mask based galois multipliers
    Patent number: 11012094
    Abstract: A programmable digital data encoder employs error correcting coding that uses Galois field multiplication logic wherein each bit of the product is produced by first applying pre-calculated mask values or mask values calculated via a processor executing code, and then applying an XOR circuit together with the mask bits from the pre-calculated or generated mask. In one example, a set of Galois field multipliers is used wherein each multiplier in the set includes a plurality of 2-bit input AND gate circuits and an m-bit input XOR gate circuit to produce a bit of the product. In one example, there are “m” mask values in a mask table wherein m is the symbol width. A different mask value is applied for each bit of the product. The mask values are each m-bits wide, and are stored, for example, in memory as a small look-up table with m m-bit entries or in m m-bit wide registers.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 18, 2021
    Assignee: ATI Technologies ULC
    Inventor: Wing-Chi Chow
  • Networked input/output memory management unit
    Patent number: 11003588
    Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 11, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Sonu Arora, Paul Blinzer, Philip Ng, Nippon Harshadk Raval
  • METHOD AND APPARATUS FOR DATA SCRAMBLING
    Publication number: 20210132675
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 6, 2021
    Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Spatial block-level pixel activity extraction optimization leveraging motion vectors
    Patent number: 10992938
    Abstract: Systems, apparatuses, and methods for implementing spatial block-level pixel activity extraction optimization leveraging motion vectors are disclosed. Control logic coupled to an encoder generates block-level pixel activity metrics for a new frame based on the previously calculated block-level pixel activity data from a reference frame. A cost is calculated for each block of a new frame with respect to a corresponding block of the reference frame. If the cost is less than a first threshold, then the control logic generates an estimate of a pixel activity metric for the block which is equal to a previously calculated pixel activity metric for a corresponding block of the reference frame. If the cost is greater than the first threshold but less than a second threshold, an estimate of the pixel activity metric is generated by extrapolating from the previously calculated pixel activity metric.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 27, 2021
    Assignee: ATI Technologies ULC
    Inventors: Mehdi Saeedi, Boris Ivanovic
  • APPLICATION PROFILING FOR POWER-PERFORMANCE MANAGEMENT
    Publication number: 20210116987
    Abstract: A processing apparatus is provided which includes memory configured to store hardware parameter settings for each of a plurality of applications. The processing apparatus also includes a processor in communication with the memory configured to store, in the memory, the hardware parameter settings, identify one of the plurality of applications as a currently executing application and control an operation of hardware by tuning a plurality of hardware parameters according to the stored hardware parameter settings for the identified application.
    Type: Application
    Filed: December 24, 2020
    Publication date: April 22, 2021
    Applicant: ATI Technologies ULC
    Inventors: Shahriar Pezeshgi, Jun Huang, Mohammad Hamed Mousazadeh, Alexander S. Duenas
  • Interposer-based damping resistor
    Patent number: 10985097
    Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 20, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Fei Guo, Feng Zhu, Julius Din, Anwar Kashem, Sally Yeung
  • LOW LATENCY WIRELESS VIRTUAL REALITY SYSTEMS AND METHODS
    Publication number: 20210112289
    Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Lei Zhang, Gabor Sines, Khaled Mammou, David Glen, Layla A. Mah, Rajabali M. Koduri, Bruce Montag
  • Methods and apparatus for optical blur modeling for improved video encoding
    Patent number: 10979704
    Abstract: Methods and apparatus of generating a refined reference frame for inter-frame encoding by applying blur parameters to allow encoding of image frames having blurred regions are presented herein. The methods and apparatus may identify a blurred region of an image frame by comparing the image frame with a reference frame, generate a refined reference frame by applying the blur parameter indicative of the blurred region to the reference frame, determine whether to use one of the reference frame and refined reference frame to encode the image frame, and encode the image frame using the refined reference frame when determined to use the refined reference frame.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: April 13, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ihab M. A. Amer, Khaled Mammou, Vladyslav S. Zakharchenko, Dmytro U. Elperin
  • ADAPTIVE OFFSET FOR VARIANCE BASED QUANTIZATION
    Publication number: 20210099705
    Abstract: A technique for determining an adaptive quantization parameter offset for a block of encoded video includes obtaining a rate control factor for the quantization parameter, determining a content-based quantization parameter factor for the quantization parameter, determining an adaptive variance based quantization offset based on content-based quantization parameter factors for a frame prior to the current frame, and combining the rate control factor, the content-based quantization parameter factor, and the adaptive offset to generate the quantization parameter.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Jiao Wang, Ying Zhang, Richard George, Edward A. Harold, Zhenhua Yang
  • Memory initialization reporting and control
    Patent number: 10964405
    Abstract: A memory module performs a memory readiness test, and reports results to a host system. The memory module initializes a status register with an initial ready time value and a memory readiness status. The memory module conducts the memory readiness test, and while conducting the memory readiness test, estimates a new ready time based on the progress of the memory readiness test. The memory module updates the ready time value in the status register based on the new ready time. After finishing the memory readiness test, the memory module updates the memory readiness status in the status register.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 30, 2021
    Assignee: ATI Technologies ULC
    Inventor: Philip Ng
  • ADAPTIVE FRAMERATE FOR AN ENCODER
    Publication number: 20210092424
    Abstract: A technique for generating encoded video in a client-server system is provided. According to the technique, a server determines that reprojection analysis should occur. The server generates reprojection metadata based on suitability of video content to reprojection. The server generates encoded video based on the reprojection metadata, and transmits the encoded video to a client for display. The client reprojects video content as directed by the server.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Applicant: ATI Technologies ULC
    Inventors: Guennadi Riguer, Ihab M. A. Amer
  • Multi-thread graphics processing system
    Patent number: 10957007
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 23, 2021
    Assignee: ATI Technologies ULC
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Hybrid render with preferred primitive batch binning and sorting
    Patent number: 10957094
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 23, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Low latency dirty RAM for cache invalidation speed improvement
    Patent number: 10956338
    Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 23, 2021
    Assignee: ATI Technologies ULC
    Inventors: Leon King Nok Lai, Qian Ma, Jimshed B. Mirza
  • Removing or identifying overlapping fragments after z-culling
    Patent number: 10943389
    Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 9, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
  • DYNAMIC CONTROL OF LATENCY TOLERANCE REPORTING VALUES
    Publication number: 20210067451
    Abstract: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: ATI Technologies ULC
    Inventor: Alexander S. Duenas