Patents Assigned to ATI Technologies ULC
-
Patent number: 11100004Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.Type: GrantFiled: June 23, 2015Date of Patent: August 24, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Gongxian Jeffrey Cheng, Mark Fowler, Philip J. Rogers, Benjamin T. Sander, Anthony Asaro, Mike Mantor, Raja Koduri
-
Patent number: 11100604Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.Type: GrantFiled: January 31, 2019Date of Patent: August 24, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jeffrey Gongxian Cheng, Ahmed M. Abdelkhalek, Yinan Jiang, Xingsheng Wan, Anthony Asaro, David Martinez Nieto
-
Patent number: 11102493Abstract: A single source image encoder encodes more than one display stream, such as multiple display streams each for a different display or multiple display streams for the same display, using multiple indexed color history (ICH) buffers. As applied to a DSC encoder, the same DSC encoder is used to encode more than one DSC compliant display stream. Multiple encoded display bitstreams are output as multiple display data streams to a plurality of displays. Such a configuration can significantly reduce the area cost of an integrated circuit that employs an image encoder since additional encoders are eliminated.Type: GrantFiled: June 13, 2019Date of Patent: August 24, 2021Assignee: ATI Technologies ULCInventors: David Glen, Nicholas Chorney
-
Patent number: 11102488Abstract: A processing system analyzes pixel activity levels of blocks of a picture at a plurality of spatial scales and/or dynamic ranges to generate a multi-scale metric that indicates how bit allocation or assignment of a given quantization parameter (QP) will affect the perceptual quality of the block. Blocks that have similar multi-scale metrics are likely to be visually similar and to benefit from similar bit allocations or QPs. Based on the multi-scale metric, an encoder encodes each block of the picture with a QP and/or a number of bits.Type: GrantFiled: May 31, 2019Date of Patent: August 24, 2021Assignee: ATI TECHNOLOGIES ULCInventors: Boris Ivanovic, Mehdi Saeedi, Edward G. Callway
-
Patent number: 11100889Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.Type: GrantFiled: February 28, 2019Date of Patent: August 24, 2021Assignee: ATI Technologies ULCInventors: Keith Lee, David I. J. Glen, Jie Zhou, Yuxin Chen
-
Patent number: 11100698Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.Type: GrantFiled: June 28, 2019Date of Patent: August 24, 2021Assignee: ATI Technologies ULCInventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Clarence Ip, Tung Chuen Kwong
-
Patent number: 11095910Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.Type: GrantFiled: December 6, 2019Date of Patent: August 17, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Lei Zhang, Ji Zhou, Zhen Chen, Min Yu
-
Patent number: 11079945Abstract: A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.Type: GrantFiled: September 20, 2018Date of Patent: August 3, 2021Assignee: ATI TECHNOLOGIES ULCInventors: Omer Irshad, Joohyun Lee
-
Patent number: 11076151Abstract: Systems, apparatuses, and methods for calculating multi-pass histograms for palette table derivation include an encoder that calculates a first histogram for a first portion of most significant bits (MSBs) of pixel component values of a block of an image or video frame. Then, the encoder selects a given number of the highest pixel count bins from the first histogram. The encoder then increases the granularity of these selected highest pixel count bins by evaluating one or more additional bits from the pixel component values. A second histogram is calculated for the concatenation of the original first portion MSBs from the highest pixel count bins and the one or more additional bits, and the highest pixel count bins are selected from the second histogram. A palette table is derived based on these highest pixel count bins selected from the second histogram, and the block is encoded using the palette table.Type: GrantFiled: September 30, 2019Date of Patent: July 27, 2021Assignee: ATI Technologies ULCInventors: Feng Pan, Wei Gao, Yang Liu, Crystal Yeong-Pian Sau, Haibo Liu, Edward A. Harold, Ying Luo, Ihab Amer, Gabor Sines
-
Patent number: 11073888Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: GrantFiled: May 31, 2019Date of Patent: July 27, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
-
Patent number: 11073889Abstract: A computing device and method controls power consumption of a graphics processing unit in the computing device by the GPU determining an allocated power for the USB device connected through a USB port, such as a USB-C port. The GPU issues allocated power information for the external USB device to cause the allocated power to be provided to the USB device and includes issuing allocated power information to a power delivery (PD) controller that is connected to a USB port. In some implementations, the GPU shifts at least a portion of the allocated power from the USB device back to the GPU in response to a usage change event associated with the USB device for improving GPU performance. The usage change event can be a disconnect event of the USB device, a power renegotiation event between the USB device and the GPU, or any other suitable usage change event.Type: GrantFiled: March 29, 2019Date of Patent: July 27, 2021Assignee: ATI Technologies ULCInventors: Vincent Cueva, Gia Tung Phan
-
Patent number: 11070829Abstract: Systems, apparatuses, and methods for reducing latency for wireless virtual and augmented reality applications are disclosed. A virtual reality (VR) or augmented reality (AR) system includes a transmitter rendering, encoding, and sending video frames to a receiver coupled to a head-mounted display (HMD). In one scenario, rather than waiting until the entire frame is encoded before sending the frame to the receiver, the transmitter sends an encoded left-eye portion to the receiver while the right-eye portion is being encoded. In another scenario, the frame is partitioned into a plurality of slices, and each slice is encoded and then sent to the receiver while the next slice is being encoded. In a further scenario, each slice is being encoded while the next slice is being rendered. In a still further scenario, each slice is prepared for presentation by the receiver while the next slice is being decoded by the receiver.Type: GrantFiled: December 16, 2019Date of Patent: July 20, 2021Assignee: ATI Technologies ULCInventors: Mikhail Mironov, Gennadiy Kolesnik, Pavel Siniavine
-
Publication number: 20210209831Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
-
Patent number: 11055242Abstract: Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.Type: GrantFiled: June 24, 2016Date of Patent: July 6, 2021Assignee: ATI Technologies ULCInventors: Gordon Caruk, Jaroslaw Marczewski
-
Patent number: 11054883Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.Type: GrantFiled: June 18, 2018Date of Patent: July 6, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Leonardo De Paula Rosa Piga, Samuel Naffziger, Ivan Matosevic, Indrani Paul
-
Publication number: 20210192087Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Guhan Krishnan, Carl K. Wakeland, Saikishore Reddipalli, Philip Ng
-
Publication number: 20210192681Abstract: A client device for use in processing reality technology content is provided. The client device comprises memory configured to store data and a processor in communication with the memory. The processor is configured to receive, from a server device via network communication channel, a video stream comprising encoded video frames and motion vector information and extract, at the client device, the motion vector information. The processor is also configured to decode the video frames, determine whether to at least one of time warp the video frames and space warp the video frames using the extracted motion vector information. The processor is also configured to display the warped video frame data.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Applicant: ATI Technologies ULCInventors: Mikhail Mironov, Gennadiy Kolesnik, Pavel Siniavine
-
Patent number: 11042495Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.Type: GrantFiled: September 20, 2019Date of Patent: June 22, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Maggie Chan, Philip Ng, Paul Blinzer
-
Publication number: 20210182121Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Amitabh Mehra, Anil Harwani, William Robert Alverson, Jerry Anton Ahrens, Jr., Charles Sum Yuen Lee, John William Abshier
-
Patent number: 11036658Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.Type: GrantFiled: January 16, 2019Date of Patent: June 15, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Vydhyanathan Kalyanasundharam, Philip Ng, Alexander J Branover, Kevin M. Lepak