Abstract: Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.

Abstract: A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences.

Abstract: A method and apparatus provides pixel information for one or more displays by producing for output on a single link, packet based pixel component multi-stream information on two or more streams. A first stream may include a portion of per-pixel component values, such as RGB pixel component values, whereas the second stream of the multi-stream may include a remaining portion of the per-pixel component values, such as a corresponding alpha value. Hence, multi-streams are employed to communicate, for example, an extended pixel component format for output to one or more displays. The multi-streams are synchronized to provide the pixel component values at a proper time for the receiving display or plurality of displays.

Abstract: A system, method and a computer program product for processing media content on a media player having direct access to hardware are provided in exemplary embodiments. When the media player is initialized, an operating system is placed into a stand-by mode that decreases power consumption on an electronic device. Instead of the operating system, a hardware pipeline processes media content. A hardware pipeline is dedicated to process a media content based on the media content type. The media content is processed using the dedicated hardware pipeline to reduce the power consumption during processing.

Abstract: A method and apparatus provides a user an interface for a file system. In one example, the method and apparatus displays the file as a visualized object, e.g., a graphical representation of the file as a real life object, receives selection of visualized objects and activates data elements represented by the visualized objects. The visualization of the file may be determined based on visualizer identification information associated with the file. For the activated data elements, the method and apparatus displays tool interfaces, in combination with the visualized objects. The tool interfaces may be selectively displayed for the activated data element base on tool identification information associated with a data type of the data element. Furthermore, the method and apparatus can process the activated data elements using the selected tool actions from different programs.

Abstract: A method for providing two or more processors access to a single command buffer is provided. The method includes receiving instructions in the command buffer from a central processor, at least one of the instructions being designated for a particular one of the two or more processors. The method also includes sending the at least one instruction to only the particular processor.

Abstract: A method and system for higher level filtering uses a native bilinear filter, typically found in a texture mapper, and combines a plurality of bilinear filter results from the bilinear filter to produce a higher level filtered texel value. A native bilinear filter is operative to generate bilinear filtered texel values by performing a plurality of bilinearly filtered texture fetches using bilinear filter fetch coordinates. The method and system combines the plurality of bilinear filtered texel values with a plurality of weights to generate the higher level filtered texel value.

Abstract: A method and apparatus provides for controlling presentation of multimedia content. In one example, the method and apparatus changes a display perspective of a multimedia presenting system that presents the multimedia content by determining an amount of display perspective adjustment based on a relative position between a user and the multimedia presenting system. According to the determined amount of display perspective adjustment, the method and apparatus issues one or more control commands that instruct the multimedia presenting system to change the display perspective. The display perspective may be changed for example by moving a display or portion thereof and/or by changing the perspective of the displayed image on the display while leaving the position of the display alone.

Abstract: The present invention provides a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex mid-size complex programmable logic devices (CPLD) or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example.

Abstract: Graphics rendering settings in a computer system are adjusted when an activity level on a bus meets a trigger condition. The graphics rendering settings of the system are returned to a previous level when the bus activity drops below a threshold. The trigger condition may be related to bandwidth usage on the bus or latency of data sent over the bus.

Abstract: A system and method for providing video compression that includes encoding using an encoding engine a YUV stream wherein Y, U and V color values are encoded in parallel and patching together the Y, U and V color streams to form a compressed YUV output stream. The encoding engine further includes encoding each color value of the YUV stream in parallel using parallel encoding engines and a control engine for controlling operation all of the encoding engines in parallel. The YUV stream has an average bits per pixel value that varies from a first value to a second value that is double the first value. The encoding engine includes encoding the YUV stream in generally the same amount of time regardless of the average bits per pixel value.

Abstract: A method of and device for providing image frames is provided. The method includes outputting portions of a first frame that have changed relative to the one or more other frames without outputting portions of the first frame that have not changed relative to the one or more other frames. Each of the portions are determined to be changed if a rendering engine has written to a frame buffer for a location within boundaries of the portion. This outputting is done in response to one or more portions of a first frame having changed relative to one or more other frames.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.

Abstract: A system includes a power management unit that may be configured to estimate the power consumed by at least a portion of each of one or more processor cores during operation of each processor core. The power management unit may be configured to generate a sum of activity values and normal weight factor values for a predetermined set of signals within each processor core to estimate the power consumed. The power management unit may also be configured to adaptively generate and selectively use new weight factor values to estimate the power consumed based upon a total measured dynamic power consumed by each processor core during operation.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract: A method and apparatus for video stream processing is implemented in a monitor scaler chip (MSC). The MSC receives the video stream and determines whether the video stream includes copy protected content. The MSC routes the video stream based upon the determination.