Patents Assigned to ATI Technologies ULC
  • Receiver and method for synchronizing and aligning serial streams
    Patent number: 8867683
    Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 21, 2014
    Assignee: ATI Technologies ULC
    Inventor: Haran Thanigasalam
  • Semiconductor chip device with polymeric filler trench
    Patent number: 8866276
    Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 21, 2014
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
  • Computing center power and cooling control apparatus and method
    Patent number: 8868944
    Abstract: Various computing center control and cooling apparatus and methods are disclosed. In one aspect, a method of controlling plural processors of a computing system is provided. The method includes monitoring activity levels of the plural processors over a time interval to determine plural activity level scores. The plural activity level scores are compared with predetermined processor activity level scores corresponding to preselected processor operating modes to determine a recommended operating mode for each of the plural processors. Each of the plural processors is instructed to operate in one of the recommended operating modes.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 21, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gamal Refai-Ahmed, Stanley Ossias, Maxat Touzelbaev
  • Device having multiple graphics subsystems and reduced power consumption mode, software and methods
    Patent number: 8868945
    Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 21, 2014
    Assignee: ATI Technologies ULC
    Inventors: Sasa Marinkovic, Phil Mummah, Mingwei Chien, Michael Tresidder, Roumen Saltchev, George Xie, Jason Long
  • Multiple display frame rendering method and apparatus
    Patent number: 8866825
    Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 21, 2014
    Assignee: ATI Technologies ULC
    Inventor: Jeffrey G. Cheng
  • Method, apparatus and machine-readable medium for apportioning video processing between a video source device and a video sink device
    Patent number: 8866971
    Abstract: To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: October 21, 2014
    Assignee: ATI Technologies ULC
    Inventor: David I. J. Glen
  • Method and apparatus for configuring multiple displays associated with a computing system
    Patent number: 8860633
    Abstract: A method and apparatus for configuring multiple displays includes determining, in connection with an image or portion thereof to be displayed on the multiple displays at the same time, whether received display preferences can be fulfilled in observance of: configuration properties of the multiple displays and configuration properties of a computing system, such as the capabilities of display controllers. The method and apparatus also determine whether a current configuration of the multiple displays to the computing system can be reconfigured such that the display preferences of the multiple displays can be fulfilled at the same time while maintaining effective configuration of a current configuration when the display preferences cannot be fulfilled, and display the images of a portion thereof on the multiple displays at the same time.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: October 14, 2014
    Assignee: ATI Technologies ULC
    Inventors: Gordon Fraser Grigor, Vladimir F. Giemborek, John E. Haberfellner
  • Method and apparatus for processing pixel depth information
    Patent number: 8860721
    Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: October 14, 2014
    Assignee: ATI Technologies ULC
    Inventors: Andrew E. Gruber, Christopher J. Brennan
  • Auto-calibrating a voltage reference
    Patent number: 8854120
    Abstract: A method and circuitry for determining a temperature-independent bandgap reference voltage are disclosed. The method includes determining a quantity proportional to an internal series resistance of a p-n junction diode and determining the temperature-independent bandgap reference voltage using the quantity proportional to an internal series resistance.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 7, 2014
    Assignee: ATI Technologies ULC
    Inventors: Grigori Temkine, Filipp Chekmazov, Oleg Drapkin
  • Self-refresh panel time synchronization
    Patent number: 8854344
    Abstract: In an embodiment, a method in a device of controlling a display is provided. The method includes transmitting a heartbeat signal in a self-refresh state. The heartbeat signal is configured to be used by a display to remain in sync with the device while the device is in the self-refresh state.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: October 7, 2014
    Assignee: ATI Technologies ULC
    Inventor: David Glen
  • Hybrid Render with Deferred Primitive Batch Binning
    Publication number: 20140292756
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Michael MANTOR, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kallio Kia, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Method and tool for virtual desktop management
    Patent number: 8850351
    Abstract: A method for providing a desktop management tool includes displaying an active desktop having at least one application window representing an active application; storing data representing a virtual desktop in memory; while displaying the active desktop, receiving non-menu-based user input representing an application-move operation between the active desktop and the virtual desktop; and associating the active application with the virtual desktop. The method may also include displaying, as part of the active desktop, a visual representation of the virtual desktop. Other examples of the described method also include displaying an enlarged view of the contents of a virtual desktop in response to additional user input. An example apparatus for implementing the described methods is also described.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 30, 2014
    Assignee: ATI Technologies ULC
    Inventors: Zak Beharie, Jason Smith
  • Integrated circuit package strip with stiffener
    Patent number: 8847383
    Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 30, 2014
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
  • Parallel synchronizing cell with improved mean time between failures
    Patent number: 8837639
    Abstract: In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 16, 2014
    Assignee: ATI Technologies ULC
    Inventor: Ioan Cordos
  • Data modification for device communication channel packets
    Patent number: 8832331
    Abstract: Techniques are disclosed relating to modifying packet data to be sent across a communication link and/or bus. Data may be modified in accordance with one or more data processing algorithms, and according to the capabilities of a destination device to receive such modified data. Lossless compression algorithms may be used on data in order to achieve a higher effective bandwidth over a particular bus or link. Encryption algorithms may be used, as well as data format conversion algorithms. One or more processing elements of a communication channel controller or other structure within a computing device may be used to modify packet data, which may be in PCI-Express format in some embodiments. A packet prefix or header may be used to store an indication of what algorithm(s) has been used to modify packet data so that a destination device can process packets accordingly.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: September 9, 2014
    Assignee: ATI Technologies ULC
    Inventor: Stephen Co
  • Sub page and page memory management apparatus and method
    Patent number: 8832382
    Abstract: A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 9, 2014
    Assignee: ATI Technologies ULC
    Inventors: David E. Mayhew, Mark Hummel
  • System and method for synchronizing threads using shared memory having different buffer portions for local and remote cores in a multi-processor system
    Patent number: 8832712
    Abstract: A method of processing threads is provided. The method includes receiving a first thread that accesses a memory resource in a current state, holding the first thread, and releasing the first thread based responsive to a final thread that accesses the memory resource in the current state has been received.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: September 9, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Michael Houston, Stanislaw Skowronek, Elaine Poon, Brian Emberling
  • Method, apparatus and machine-readable medium for handling interpolated video content
    Patent number: 8830393
    Abstract: Spatial or temporal interpolation may be performed upon source video content to create interpolated video content. A video signal including the interpolated video content and non-interpolated video content (e.g. the source video content) may be generated. At least one indicator for distinguishing the non-interpolated video content from the interpolated video content may also be generated. The video signal and indicator(s) may be passed from a video source device to a video sink device. The received indicator(s) may be used to distinguish the non-interpolated video content from the interpolated video content in the received video signal. The non-interpolated video content may be used to “redo” the interpolation or may be recorded to a storage medium.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: September 9, 2014
    Assignee: ATI Technologies ULC
    Inventor: David Glen
  • Variable-length code decoder
    Patent number: 8824819
    Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: September 2, 2014
    Assignee: ATI Technologies ULC
    Inventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Stephen C. Hale
  • Accelerated processing unit debugging using a graphics processing unit centric debug core
    Patent number: 8819489
    Abstract: An Accelerated Processing Unit (APU) comprising a central processing unit (CPU) core portion and a graphics processing unit (GPU) core portion coupled to the CPU core portion. The GPU core portion includes a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: August 26, 2014
    Assignee: ATI Technologies ULC
    Inventor: Navin Patel