Abstract: A communications controller includes a physical interface and an internal transmit and receive circuit. The physical interface has a port for connection to a communication medium, an input, and an output, and operates to receive a first sequence of data bits from the input and to transmit the first sequence of data bits to the port, and to receive a second sequence of data bits from the port and to conduct said second sequence of data bits to the output. The internal transmit and receive circuit is coupled to the physical interface, and has an internal architecture to conduct a first plurality of symbols at a first rate in a low frequency mode and a second plurality of symbols at a second rate in a low latency mode, wherein the first plurality is greater in number than the second plurality, and the second rate is higher than the first rate.

Abstract: A method and apparatus for transcoding video data decodes video that is encoded in the first format and produces decoded data blocks that include decoded tile data such that each decoded block includes pixel data for multiple display lines. The method and apparatus performs a linear write operation on the decoded data block by controlling storing of the decoded data block rows in consecutive linear addresses in memory such that one line of memory comprises decoded data for multiple display lines from the same block. The method and apparatus fetches the line of memory and re-encodes the data into a data block format, In one example translation of the fetched line of memory back into the original decoded data block format is performed for re-encoding such that the block of data includes data for multiple display lines. The video data is re-encoded to the second format using the decoded data block that was translated from the fetched line of memory.

Abstract: One or more specialized field programmable modules (e.g. CPLD and FPGA blocks) and their programming interface are embedded into a processing system (e.g. a CPU, GPU, APU and/or chipset). The field programmable modules are in-system programmable, in contrast to the application specific integrated circuit (ASIC) modules that perform the core functions of the processing system. The programmable flexibility of the field programmable modules can have various benefits during different stages of the integrated circuit life cycle for the processing system, such as reconfigurable interface bridging and two-way I/O expansion.

Abstract: A system and method for providing viewer preferences on a display device are presented. An embodiment includes a storage medium for storing preset viewer preferences, each preference being categorized based on one of a plurality of viewers, a processor that accesses the storage medium and acquires the stored preset viewer preference for a given one of the plurality of viewers, and a display device that provides content to the viewer in accordance with the viewer's preferences using at least one optical element.

Abstract: A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: A scalable high throughput video encoder is described herein. A plurality of dedicated, hardware video encoders runs in a staggered, parallel architecture, where each video encoder encodes a video frame and the stagger or delay is a programmable number of macroblock rows. In an example method, after a first video encoder finishes encoding the first x macroblock rows of a frame, the first video encoder signals a second video encoder to start encoding a macroblock row of a next unprocessed frame. Both video encoders continue encoding in parallel in a synchronized, staggered manner. At the end of the frame, the first video encoder starts encoding x macroblock rows of another unprocessed frame.

Abstract: A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A method and system of testing pixels output from a pixel generation unit under test includes generating pixels from the pixel generation unit under test using a first test data pattern to generate pixel information. The method and system also generate a per pixel error value for a pixel from the unit under test that contains an error based on the pixel by pixel comparison with pixel information generated substantially concurrently with pixels by a different unit using the first test data pattern. If desired, corresponding pixel screen location information (e.g., x-y location) can also be determined for the pixel that has the error. The per pixel error and x-y location information can be displayed.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.

Abstract: Methods and apparatus for dynamically adjusting a power level of an electronic device (100) are disclosed. In an embodiment, an electronic device (100) receives a usage pattern of the electronic device (100) (e.g., typically used 9:00 AM to 5:00 PM on weekdays). The electronic device (100) then dynamically adjusts a wake up timer (204) associated with the electronic device (100) based on the usage pattern (e.g., expire at 8:50 am the next morning, which is 10 minutes before usage typically resumes for that day). In response to an expiration of the dynamically adjusted wake up timer (204), the electronic device (100) increases the power level of the electronic device (100) (e.g., transition from hibernate mode to standby mode, possibly via other intervening power modes, for faster startup in anticipation of resumed usage).

Abstract: A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location.

Abstract: A reference voltage generator is provided. In an example, the reference voltage generator includes a temperature-dependent device, a processing module configured to process a digital representations of first and second voltages derived from the temperature-dependent device and a reference voltage to determine a value, and a digital to analog converter (DAC) configured to generate a reference voltage based on the value. The first voltage is proportional to absolute temperature (PTAT) and the second voltage is complementary to absolute temperature (CTAT) and the reference voltage is substantially independent of absolute temperature in an operating temperature range of the reference voltage generator.

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

Abstract: A charging system having a charging device with a groove for receiving a mobile/portable device for charging is provided having a magnetic core located in a housing of the charging device with the magnetic core having a base and two legs that are located around the groove. A coil is wrapped around the base and a driver circuit is connected to the coil as well as to an external power source. A power receiver is located in a mobile/portable device that can be placed in the groove in the charging device. The power receiver includes a receiver magnetic core as well as a receiving coil wrapped around the receiver magnetic core for receiving an inductive current from the charging device. A charging circuit is connected to the receiving coil and adapted to be connected to the battery of the mobile/portable device for charging.

Abstract: A method and apparatus provides for enhanced processing of 3D graphics data such as image-based 3D graphics data. The image-based 3D graphics data may include data defining texture, bump, normals, displacement, etc for underlying objects. In one example, the method and apparatus compresses image-based 3D graphics data as one or more frames contained in one or more videos and decompresses the compressed 3D graphics data using video acceleration hardware provided by a GPU. In another example the method and apparatus may also selectively control caching of image-based 3D graphics data. Before so cached, the image-based 3D graphics data may be compressed as one or more frames contained in one or more videos using video acceleration hardware provided by the GPU to achieve efficient usage of cache space.

Abstract: A device receives a request to use a software program, determines a comparison indicator based on receiving the request, and determines whether a license for the software program is valid based on a license validity indicator, stored in a secure environment, and the comparison indicator. The device permits execution of secure code stored in the secure environment when the license is determined to be valid, and prevents execution of the secure code stored in the secure environment when the license is determined to be invalid.

Abstract: A method and apparatus for correcting a rotation of a video frame are described. According to a method, an amount of the rotation of the video frame with respect to a reference is determined. The rotation of the video frame is corrected based at least in part on the detected amount of the rotation of the video frame.