Abstract: A method of operating a device is provided. The method includes transitioning the GPU to a substantially disabled state in response to a first received signal, and generating, while the GPU is in the substantially disabled state, a response signal in response to a second received signal. The response signal is substantially similar to a second response signal that would be generated by the GPU in a powered state in response to the second received signal.
Type:
Application
Filed:
February 26, 2010
Publication date:
March 10, 2011
Applicants:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Inventors:
Oleksandr KHODORKOVSKY, Ali Ibrahim, Phil Mummah
Abstract: Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.
Type:
Application
Filed:
March 8, 2010
Publication date:
March 10, 2011
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
David I.J. GLEN, Philip J. Rogers, Gordon F. Caruk, Gongxian Jeffrey Cheng, Mark Hummel, Stephen Patrick Thompson, Anthony Asaro
Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.
Type:
Application
Filed:
January 28, 2010
Publication date:
March 10, 2011
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Abstract: A method of power management is provided. The method includes detecting an event, assign a first responsibility to a first graphics processing unit (GPU) and a second responsibility to second GPU, and changing a power state of the first and second GPUs based on the first and second responsibilities, respectively. The first responsibility is different from the second responsibility.
Abstract: Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.
Type:
Application
Filed:
April 16, 2010
Publication date:
March 10, 2011
Applicants:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Michael J. MANTOR, Jeffrey T. Brady, Christopher L. Spencer, Daniel W. Wong, Andrew E. Gruber
Abstract: The present invention provides an analysis method that uses error metrics to determine whether an image is suitable for compression. One embodiment of the present invention can make the determination in real-time. In one embodiment, analysis methods based on four error metrics are used to determine whether a compressed image should be used. The first metric is a signal-to-noise (SNR) error metric that prevents compressed images with low SNR from being used to represent original images. Another metric is detecting the geometric correlation of pixels within individual blocks of the compressed images. The third metric is used to determine whether color mapping in the compressed images are well-mapped. A final metric is a size metric that filters images smaller than a certain size and prevents them from being compressed. As most analysis methods are integral parts of the compression process, the present invention incurs little cost collecting error metric data.
Type:
Grant
Filed:
October 29, 2002
Date of Patent:
March 8, 2011
Assignee:
ATI Technologies ULC
Inventors:
David Oldcorn, Andrew Pomianowski, Raja Koduri
Abstract: An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.
Type:
Grant
Filed:
August 15, 2007
Date of Patent:
March 8, 2011
Assignee:
ATI Technologies ULC
Inventors:
Aris Balatsos, Charles Leung, Siva Raghu Ram Voleti
Abstract: A method detects by a display driver logic, inactivity between the display driver logic and a display logic, and deactivates an auxiliary channel by the display driver logic, wherein the auxiliary channel is between the display driver logic and the display logic. The method also detects, by the display driver logic via the auxiliary channel, a required operating mode capability of a display; and determines a minimum number of connection lines needed between the display driver logic and the display logic, to operate the display in the required operating mode capability. A display driver logic includes a connection port suitable for operative connection to a display logic, wherein the display drive logic is operative to detect inactivity between the display driver logic and the display logic, and deactivate an auxiliary channel between the display driver logic and the display logic.
Abstract: An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.
Type:
Application
Filed:
August 24, 2010
Publication date:
March 3, 2011
Applicant:
ATI TECHNOLOGIES ULC
Inventors:
David I.J. Glen, Collis Quinn Carter, Natan Shtutman, Gabriel Abarca, Jonathan Wang
Abstract: An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.
Type:
Application
Filed:
August 24, 2010
Publication date:
March 3, 2011
Applicant:
ATI TECHNOLOGIES ULC
Inventors:
David I.J. Glen, Collis Quinn Carter, Natan Shtutman, Ngar Sze Nancy Chan, Michael Foxcroft
Abstract: An electrical connector, such as a circuit board connector, includes a first group or subassembly of electrical contacts physically separate from an adjacent and second group or subassembly of contacts. The first group of electrical contacts and second group of electrical contacts each include a row of lower contacts and upper contacts. The second group of electrical contacts has an identical but mirrored configuration as the first group of electrical contacts.
Abstract: A method is disclosed that provides, by mapping logic, output to a selected display of a plurality of displays forming an arrangement, where the selected display provides a visual indication in response to the output. The visual indication indicates that the selected display is ready to be mapped to an image data portion corresponding to the selected display's physical position within the arrangement. The method maps the image data portion to the selected display. The image data portion is stored in a frame buffer, and is mapped in response to input indicating the selected display's physical position. The frame buffer stores a single large surface image as a plurality of image data portions, where each image data portion is mapped to a corresponding display of the plurality of displays. An apparatus is also disclosed, that operates in accordance with the method.
Type:
Application
Filed:
August 24, 2009
Publication date:
February 24, 2011
Applicant:
ATI Technologies ULC
Inventors:
Stephen J. Orr, Christina M. Elder, Wenzhan Xie, Jianping Ji
Abstract: A circuit includes a plurality of display path circuits and a timing and frame synchronization circuit. The timing and frame synchronization circuit aligns a first blanking interval of first timing information provided by a first of the display path circuits for a first display based on a second blanking interval of second timing information provided by a second of the display path circuits for a second display.
Abstract: A digital data transmitting device is disclosed having differential signaling circuitry, a current source controller and a pair of transistor-implemented current sources is disclosed. The current source controller generates a current source control signal based on a detected mode of operation of the differential signaling circuitry. The pair of transistor-implemented current sources selectively generate source currents to adjust the output voltage levels as the differential output terminals in response to the current source control signal. The digital data transmitting device may also include a current bulk biasing circuit that generates a current source bulk biasing signal such that when the differential signaling circuitry is in one mode of operation, the current source bulk biasing signal retards currents leakage across the pair of transistor-implemented current sources.
Abstract: In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.
Abstract: An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described.
Abstract: An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure.
Abstract: When a physical change (e.g. a change in screen orientation) is detected at a display device that is attached to a graphics subsystem of a host device and on which images are currently being displayed, a hot plug detect signal may be provided to the graphics subsystem. In response, the graphics subsystem may adjust its processing of images to account for the physical change (e.g. the image may be rotated). The display device may communicate data representative of the physical change to the graphics subsystem. The graphics subsystem may use this data to determine how its processing of images should be adjusted. The data may be communicated over an I2C bus regardless of whether a hot plug detect signal is provided.
Abstract: A video decoding method and apparatus receives a motion compensation shader command, such as a packet, for a programmable shader of a 3D pipeline, such as programmable vertex shaders and pixel shaders, to provide motion compensation for encoded video, and decode the encoded video using the programmable shader of the 3D pipeline. As such, the programmable shader of a 3D pipeline is used to provide motion compensated video decoding as opposed to, for example, dedicated hardware, thereby, among other advantages, eliminating the need for the dedicated hardware.
Abstract: A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m?n is disclosed. The method includes forming (m?n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.
Type:
Application
Filed:
July 31, 2009
Publication date:
February 3, 2011
Applicant:
ATI Technologies ULC
Inventors:
Andrew Leung, Roden Topacio, Liane Martinez, Yip Seng Low