Abstract: A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters.

Abstract: Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first dielectric layer over a first conductor structure of a semiconductor chip and forming a first opening in the first dielectric layer to expose at least a portion of the conductor structure. The first opening defines an interior wall that includes plural protrusions. A solder structure is coupled to the first conductor structure such that a portion of the solder structure is positioned in the first opening.

Abstract: A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel.

Abstract: A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information.

Abstract: A method and apparatus for hierarchical Z buffering stenciling includes comparing an input tile Z value range with a hierarchical Z value range and a stencil code. The method and apparatus also updates the hierarchical Z value range and stencil code in response the comparison and determines whether to render a plurality of pixels within the input tile based on the comparison of the input tile Z value range with the hierarchical Z value range and stencil code. In determining whether to render the tile, a stencil test and a hierarchical Z value test is performed. If one of the test fails, the tile is killed as it is determined that the pixels are not visible in the graphical output. If the stencil test passes and the hierarchical Z test passes, the pixels within the tile are rendered, as it is determined that the pixels may be visible.

Abstract: A method includes displaying, on a single large surface display, a first moveable and second fixed portion of a visual test object. The first portion is displayed on the display to be configured and the second portion is displayed on at least one neighboring display, and are shown in a relative orientation adjacent to a common border formed by a first bezel of the display to be configured and a second bezel of the at least one neighboring display, and any space in between. The method obtains bezel compensation configuration information in response to input aligning the first portion with the second portion. A user may provide input by moving the first portion to align it with the second portion so that a third portion of the visual test object appears hidden by the common border. The object therefore appears aligned “behind” the bezel.

Abstract: Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In a proposed embodiment, at least one heat pipe is used to transfer heat from the condensation portion of a vapor chamber to cool a bottom portion of a finned heat dissipation space and transfer the heat to a colder location on the heat fins. In another proposed embodiment, the water vapor chamber is placed in a heat sink and is adapted to thermally connect to at least one heat pipe.

Abstract: A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. The integration between the first latch loop and the second latch loop is such that the second latch loop creates an input-output connection if transmission gates in the second latch loop are conductive, and disables the input-output connection if the transmission gates are not conductive.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: A three-dimensional processing circuit includes a multi-stream 3D image sender that produces packet based multi-stream information that includes a first stream that has first eye view information, such as left eye frame information and a second stream that includes corresponding second eye view information, such as right eye frame information, for display on a single display, wherein each stream comprises a same object viewed from differing view perspectives. In one example, the multi-stream information is communicated as packetized data over a single cable, for example wherein a packet includes both the left eye and right eye information. In addition, the encoder provides as part of the multi-stream information, control information indicating that the first and second streams are for a single display. In one example, the multi-streams are communicated concurrently so that the single display can display stereoscopic left and right eye frame information.

Abstract: A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In an embodiment, the vapor configuration is modified to include fins that define a cross-flow heat exchanger where the vapor from the vapor chamber serves as the fluid in the vertical cross-flow in the heat exchanger and natural or forced cooling air serves as the horizontal cross-flow for the heat exchanger.

Abstract: A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like.

Abstract: A method and apparatus that partitions a single display's viewable area into at least two virtual viewable areas, and emulates the at least two virtual viewable areas as at least two emulated physical displays with an operating system such that the operating system behaves as if interfacing with at least two actual independent physical displays. The method provides the operating system with generated display identification data (such as “EDID”) for each of the emulated physical displays in response to a query from the operating system. The method and apparatus also receive notification of an interrupt (where the interrupt corresponds to the single physical display), and reports to the operating system with at least two sets of interrupt reporting information, corresponding to the at least two emulated physical displays, as if two interrupts were received. The operating system is thereby “faked” into acting as if two physical displays are in operation.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A digital interface device is provided for facilitating key encryption of a digital signal which is communicated from a computer system to an associated peripheral device, such as a digital display device. The digital interface device has a digital output, digital output formatting circuitry associated with the output and a non-volatile RAM for storing a basic input/output system (BIOS) for, inter alia, controlling digital output formatting. The interface device is configured such that the non-volatile RAM has a specific addressable write-protectable area allocated for storing an encryption key flag at a flag address along with encryption key data. The write-protectable area is rendered read-only when a predetermined flag value is stored at the flag address.

Abstract: A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an interrupt should be generated to service the event. A timer at the peripheral device is adjusted as needed to maintain a value within the acceptable period. Upon expiry of the timer a single interrupt is generated to a processor interconnected to the peripheral device. In response to the single interrupt, software code is executed on the processor to service un-serviced hardware events for which an indicator has been recorded.

Abstract: A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences.

Abstract: An integrated circuit includes first and second voltage domains. The first voltage domain is associated with a positive voltage supply grid and the second voltage domain is associated with a selectably on voltage supply grid. A switch is used to selectably switch on and off the selectably on voltage supply grid to power the second voltage domain. A buffer cell cluster of at least on initial buffer cell and a pair of insulator cells is coupled to the positive voltage supply grid electrically independent of the nodes of a switch and is capable of buffering a feed-through signal having a logic one voltage level defined substantially at the voltage level of the positive voltage supply grid. The buffer cell cluster has two distal ends. buffer cell cluster, at one distal end, is coupled to a first insulator cell of the pair of cells while, at the other distal end, the buffer cell cluster is coupled to a second insulator cell of the pair of the cells.