Abstract: Software for dynamically previewing changes to hardware driver settings for a graphics adapter is disclosed. Changes to the driver settings are dynamically previewed by forcing an executable graphics program module to load hardware parameter settings as changed, and drawing a region reflecting the changes using the executable graphics program library. The graphics program module may be forced to load new settings as a result of being newly instantiated. Conveniently, a preview region reflecting changes may be drawn in place of an already existing preview region.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels.

Abstract: Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed.

Abstract: An apparatus includes a chrominance and luminance module. The chrominance and luminance module obtains display characteristics of each of a plurality of displays. The chrominance and luminance module selectively adjusts, on a per display basis, chrominance and luminance for each of the displays based on the display characteristics. In one example, the displays collectively display a single large surface.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m?n is disclosed. The method includes forming (m?n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.

Abstract: In a device comprising at least two graphics processors, a determination is made that the device has switched from a first or current graphics processor to a second or target graphics processor. At least a portion of settings corresponding to the first graphics processor are identified for application to the second graphics processor, and settings of the second graphics processor are updated based on these transferable settings. The transferable settings may be identified based on a change indicator(s) that signals which settings corresponding to the first graphics processor have been changed. Where necessary, certain ones of the transferable settings may have a translation or transformation applied thereto. Subsequent transitions in the active graphics processor may cause a similar transfer of settings to occur. In one embodiment, transitions between graphics processors may be caused by a change in power condition of the device.

Abstract: A method and apparatus for storing a compressed video stream or an uncompressed video stream is disclosed. The uncompressed video stream may be ZOOM VIDEO data. The compressed video stream may be a TRANSPORT STREAM data from a High Definition Television (HDTV) broadcast. A video graphics adapter is configured to properly receive one of the two types of video data. The received data and control signals are monitored to provide a second set of control of data signal which are used by a packer and an window control to provide data of a predetermined width and control to an address generator. The data is buffered within a graphics memory such as a frame buffer. The graphics memory can be written to system memory when full, or accessed by the system memory controller during the fill operation if a multi-ported memory is used.

Abstract: A remote connection system capable of generating a wake-up command and method thereof include a remote connector with a power supply input receiver capable of being connected to a power source and further capable of receiving a power supply for the purpose of powering the remote connector. The remote connector further includes a plurality of input ports allowing the coupling of a connector thereto and providing for the transmission of information thereacross. The remote connector further includes a wireless receiver capable of wirelessly receiving a wireless command and a transmitter capable of generating the wake-up command in response to the wireless command. The remote connector further includes a remote device capable of receiving a user input command, generating the wireless command and thereupon wirelessly transmitting the command to the wireless receiver of the remote connector.

Abstract: A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache.

Abstract: Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.

Abstract: A method and apparatus for selectively charging a secondary voltage rail includes selectively and partially charging a secondary voltage rail using at least one soft start power gate switch and using an initial power control indicator. The partially charged secondary voltage rail is selectively charged, using at least one main power gate switch, based on the initial power control indicator and a detected voltage on the secondary voltage rail. When the initial power control indicator is in a state representative of an initial power up command and when the detected voltage is greater than or equal to a predetermined voltage level, at least one main power gate switch is closed thereby charging the secondary voltage rail.

Abstract: Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.

Abstract: A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences.

Abstract: A device for rapidly instituting an active mode of a digital-television enabled system, the system including a first, volatile memory configured to load and store software instructions, includes: an input configured to receive first digital audio and video information; a first output configured to convey second audio and information toward a display regarding the first audio and video information; at least one second output configured to convey commands to, and receive information from, the first memory; and a processor configured to perform functions in accordance with software instructions stored in first and second memories and to cause the first memory to load software instructions for provision to the processor such that first instructions for processing at least one of the first audio information and the first video information are loaded and stored by the first memory with a higher priority than second instructions for performing other functionality.

Abstract: A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels.