Abstract: The present application discloses a method for communicating between at least two different levels of software components. The method includes establishing a command set common to the at least two different levels of software components. Additionally, the method includes providing a command decoder operable by both of the at least two levels of software components, the command decoder configured to decode the command set. By providing a common command set between different levels of software components, such as a software driver and a BIOS, where the commands within the command table are interpreted and executed by an identical command decoder that interprets and executes the same command tables, this ensures that the same features or functions are implemented or executed in the same way across different levels of the software components. Accordingly, redundant implementation of the same functions by different software components is eliminated.

Abstract: A method for determining the appearance of a pixel includes receiving fragment data for a pixel to be rendered; storing the fragment data; and determining an appearance value for the pixel based on the stored fragment data, wherein a portion of the stored fragment data is dropped when the number of fragment data per pixel exceeds a threshold value enabling large savings in memory footprint without impacting perceivably on the image quality. A graphics processor includes a rasterizer operative to generate fragment data for a pixel to be rendered in response to primitive information; and a render back end circuit, coupled to the rasterizer, operative to determine a pixel appearance value based on the fragment data by dropping the fragment data having the least effect on pixel appearance.

Abstract: A disclosed method comprises obtaining location data including geographic coordinates; searching stored digital video broadcast network requirements data corresponding to the location data; and tuning to a digital video broadcast network channel indicated by the digital video broadcast network requirements data. The step of obtaining location data may further comprise obtaining Global Positioning System (GPS) data; and searching using the GPS data. An integrated circuit includes tuner logic, operative to tune to, and receive, a digital video broadcast network channel in response to a command; location data logic to receive location data; digital video broadcast network reception requirements logic to obtain location data from the location data logic and search stored digital video broadcast network requirements data corresponding to the location data, and send the command to the tuner logic to tune to a digital video broadcast network channel indicated by the digital video broadcast network requirements data.

Abstract: A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages.

Abstract: A circuit includes a circuit identification storage module and a control module. The circuit identification storage module stores circuit identification information. The control module receives the circuit identification information and in response thereto selectively performs a secure boot procedure or a test boot procedure. The control circuit performs the secure boot procedure when the circuit identification information indicates that the circuit is a production circuit. The control circuit performs the test boot procedure when the circuit identification information indicates that the circuit is a test circuit. A related method is also disclosed.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A system includes a processing device, at least one data processing module, and a security control module. The security control module is operatively connected to both the processing device and the data processing module. The security control module is operative to control access to a protected register that is associated with the at least one data processing module. As such, the security control module operates as a firewall or filter to allow or deny access to a protected register. Security-unaware data processing module are therefore secured in the system at a central location while eliminating the need to use only security-aware data processing module. A method for securing data processing modules, including security-unaware data processing module, is also disclosed.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.

Abstract: A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host.

Abstract: The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2^n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.

Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

Abstract: The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A method comprising determining that a minimum operation level of an integrated circuit (100) has been reached and that a sleep mode is therefore allowable; storing minimum operation context information to a RAM (115) in response to determining that the minimum operation level has been reached; switching to a sleep mode code (116) in the RAM (115); and transferring memory control from a primary memory controller (104) to a secondary memory controller (112) wherein only the secondary memory controller (112) controls the RAM (115). The method may include storing the sleep mode code (116) and a wakeup code (117) in the RAM (115) in response to determining that sleep mode is allowable, where the wakeup code (117) restores a minimum operation context using the minimum operation context information stored in the RAM (115). The method may also include placing a plurality of integrated circuit power islands into a sleep mode and leaving a secondary memory controller power island (109) in a normal power mode.

Abstract: In a power management scheme for a power-consuming (e.g. electronic) device, one of multiple predefined operating parameter sets is selected. Each of the sets comprises multiple operating parameter values for the device. Examples of operating parameters include clock frequency or voltage for example. The selection may be responsive to the detection of an event which warrants a change in a current power consumption state of the device. Any operating parameter value in the selected set that would prevent the device from meeting current operating demands is modified to a new value. The new value may be taken from another operating parameter set. The modified set of parameters is applied to the device in order to change the current power consumption state of the device.

Abstract: The present disclosure relates to thermal management apparatus for a circuit substrate having heat generating components mounted on one or both sides thereof. The apparatus and method includes a circuit assembly having a first thermally conductive layer disposed on each side of the circuit substrate and being thermally coupled to one or more heat generating components of the circuit substrate. The apparatus and method includes a second thermally conductive layer disposed on each side of the circuit substrate and being thermally coupled to the first thermally conductive layer. The first thermally conductive layer and the thermally conductive layer can be shaped, sized, and/or configured to provide cooling of the one or more heat generating components disposed on each side of the circuit substrate by transferring and spreading the heat to the outside of the circuit assembly.