Abstract: An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.

Abstract: A digital rights management system includes an authentication module and a decryption module. If desired, the modules can be implemented in separate integrated circuits. The authentication module retrieves authentication information for protected content and powers down after the authentication information is retrieved. The decryption module decrypts the protected content based on the authentication information while the authentication module is powered down.

Abstract: The various embodiments herein disclosed include a method wherein an integrated circuit (100) may receive a code image from an external device (127), encrypt the code image using a cryptographic logic (113) with a Hardware Unique Key to create a Hardware Unique Code Image (119) where the Hardware Unique Key is inaccessible to the external device (127). The integrated circuit (100) will then store the Hardware Unique Code Image wherein the Hardware Unique Code Image is executable only after decryption using the Hardware Unique Key. The method also includes sending a command to a cryptographic logic (113) to request decryption of the Hardware Unique Code Image by the cryptographic logic (113) using the Hardware Unique Key and executing the Hardware Unique Code Image by the boot software (103) after the decryption.

Abstract: A device and method are provided that generate an early warning disconnect signal from an electrical connector supplying external power to a connected device. The connected device includes an early warning disconnect power management circuit, operational to generate power consumption control information in response to generation of the early warning disconnect signal from the electrical connector. In one example, the electrical connector includes a lock release mechanism and a signaling mechanism, the signaling mechanism is operationally coupled with the lock release mechanism and configured to generate the early warning disconnect signal from the electrical connector to the connected device prior to the lock release mechanism being in an unlocked state.

Abstract: A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.

Abstract: An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected object data of the digital image and image object library data associated with image descriptor library data. An automated library user interface presents selectable matched object descriptor data associated with the image descriptor library data when a recognition match occurs between the selected object data of the digital image and the image descriptor library data. In response, the automated library user interface provides user feedback data to confirm that the image descriptor library data corresponds with the selected object data of the digital image, or entered descriptor data if no match or an incorrect match occurs, to create library descriptor associated image data.

Abstract: A block-based image compression method and encoder/decoder circuit compresses a plurality of pixels having corresponding original color values and luminance values in a block according to different modes of operation. The encoding circuit includes a luminance-level-based representative color generator to generate representative color values for each of a plurality of luminance levels derived from the corresponding luminance levels to produce at least a block color offset value and a quantization value. According to mode zero, each of the pixels in the block is associated with one of the plurality of generated representative color values to generate error map values and a mode zero color error value. According to mode one, representative color values for each of at least three luminance levels are also generated to produce at least three representative color values, corresponding bitmap values and a mode one color error value.

Abstract: A method and apparatus are disclosed wherein the horizontal and vertical variances of the pixels of an image are determined to calculate a noise measurement in a received image.

Abstract: A device and method for controlling generation of a final pixel utilizes a conditional statement, referred to as an IF_NEIGHBOR statement, which when compiled, causes a programmable pixel shader to perform mip map texture lookups even if a pixel of interest does not meet the condition of the conditional statement. As such, any neighboring pixels needed for mip map selection have their associated shader code guaranteed to execute even though the pixel of interest may fail the conditional portion of the conditional statement. The device and method executes texture address calculations for pixels within a region and for pixels outside of a region but only those necessary to determine the mip map level corresponding to a pixel within the region. Execution of shader code for a current pixel is executed if any of the surrounding neighboring pixels meet the desired condition even if the current pixel does not meet the condition.

Abstract: In an embodiment, a bias generator circuit comprises a first circuit and a second circuit. The first circuit includes a first input coupled to a voltage source and a first output that provides a first output current having a substantially non-zero temperature coefficient. The first circuit comprises a first transistor and a second transistor. The second circuit includes a second input that receives the first output current from the first circuit and a second output that provides a second output current. The second circuit comprises a third transistor and a fourth transistor. The second output current has a substantially zero temperature coefficient dependent on (i) a difference between an effective channel size of the first transistor and an effective channel size of the second transistor, and (ii) a difference between an effective channel size of the third transistor and an effective channel size of the fourth transistor.

Abstract: A target pixel and surrounding pixels corresponding to the target pixel are obtained from a digitally represented image. A bilateral high pass filtering kernel is determined based at least in part upon the target pixel and the surrounding pixels. A high pass spatial filtering kernel is provided and multiplied with the high pass photometric filtering kernel to provide a bilateral high pass filtering kernel. The resulting bilateral high pass filtering kernel is thereafter applied to the target pixel and the surrounding pixels to provide a filtered pixel. When it is desirable to combine noise filtering capabilities with sharpening capabilities, the bilateral high pass filter of the present invention may be combined with a bilateral low pass filtering kernel to provide a combined noise reduction and edge sharpening filter. The present invention may be advantageously applied to a variety of devices, including cellular telephones that employ image sensing technology.

Abstract: A method to generate super-resolution images using a sequence of low resolution images is disclosed. The method includes generating an estimated high resolution image, motion estimating between the estimated high resolution image and comparison images from the sequence of low resolution images, motion-compensated back projecting, and motion-free back projecting that results in a super resolved image. A corresponding system for generating super-resolution images includes a high resolution image estimation module, a motion estimating module, a motion-compensated back projection module, a motion-free back projection module, an input interface, and an output interface.

Abstract: A method for rendering pixels for display includes generating stencil values on a per pixel basis for storage in stencil buffer memory; selecting a group of stencil values that represent a block of pixels; generating compressed stencil data associated with the group of stencil values; and performing stencil testing on a corresponding incoming block of pixels using the compressed stencil data.

Abstract: A video processing device comprises a display interface coupleable to a display device and a display controller configured to transmit a video signal via an output node of the display interface. The video signal comprises an active segment comprising video information and an inactive segment comprising synchronization information. The video processing device further comprises a display detector configured to determine whether the display device is coupled to the display interface based on a comparison of a first voltage at the output node during transmission of the inactive segment to a second voltage.

Abstract: A method comprises disabling a video digital-to-analog converter (DAC) that is configured to provide an output current representative of a video signal to an output node of an accessory connector in an enabled state. The accessory connector is coupleable to an accessory device. The method further comprises determining, while the video DAC is disabled, whether the accessory connector is coupled to the accessory device based on a voltage at the output node while the output node is connected to the first voltage reference via a resistor having a resistance.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

Abstract: A method and system of testing pixels output from a pixel generation unit under test includes generating pixels from the pixel generation unit under test using a first test data pattern to generate pixel information. The method and system also generate a per pixel error value for a pixel from the unit under test that contains an error based on the pixel by pixel comparison with pixel information generated substantially concurrently with pixels by a different unit using the first test data pattern. If desired, corresponding pixel screen location information (e.g., x-y location) can also be determined for the pixel that has the error. The per pixel error and x-y location information can be displayed.

Abstract: A method and circuit for generating an M-bit digital dither signal with a substantially uniform probability density function and high-pass spectrum are disclosed. The circuit includes a linear feedback shift register (LFSR) with N storage elements where N>M, and a high-pass filter. The method involves sampling at least M storage elements of the LFSR with each clock cycle to form an M-bit LFSR output and high-pass filtering and the M-bit LFSR output to provide the M-bit dither signal.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters.