Abstract: A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.

Abstract: In a process, a power mode indicator is transmitted from a content server and is received by a Portable Communication Device (PCD). The indicator is indicative of a power mode potentially available to a circuit block in the PCD. The circuit block exhibits different levels of power consumption when operated in different power modes and is operated in the indicated power mode in response to the received power mode indicator. The content server may be a stream server. The circuit block may be operated in the power mode to receive/process a data stream.

Abstract: A method and apparatus for enhancing an input image to produce a contrast enhanced output image is disclosed. The method involves producing a contrast value for each pixel in the input image, the contrast value being proportional to an intensity gradient between each respective pixel and at least one pixel adjacent the respective pixel. The method also involves selecting pixels in the input image having respective contrast values that meet a first criterion, thereby forming a selected plurality of pixels and producing a frequency distribution of intensity values of the selected plurality of pixels. The method further involves selecting at least one range of intensity values in the frequency distribution that meet a second criterion, thereby producing a selected range of intensity values for enhancement.

Abstract: Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.

Abstract: An integrated circuit suitable for power conservation is disclosed. The circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.

Abstract: A method of directing an audio signal to an intended user by a remote-control device coupled to an audio/video device is described. The remote-control device sends an instruction to the audio/video device to transmit an audio signal. The remote-control device receives the audio signal and process the audio signal to generate a directional audio. The directional audio is then routed to an intended user such that the directional audio signal is audible to the intended user, other recipients in the vicinity.

Abstract: A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew.

Abstract: A method and device for enhanced rendering providing reduced memory bandwidth requirements in a graphics processor. In the rendering process, a classification buffer of limited bit length is used for classifying the pixels. Based on the classification, a decision on the pixel color may be made without accessing the multi-sample buffer for a portion of the pixels. This reduces the memory bandwidth requirements.

Abstract: In an embodiment, a bias generator circuit comprises a first circuit and a second circuit. The first circuit includes a first input coupled to a voltage source and a first output that provides a first output current having a substantially non-zero temperature coefficient. The first circuit comprises a first transistor and a second transistor. The second circuit includes a second input that receives the first output current from the first circuit and a second output that provides a second output current. The second circuit comprises a third transistor and a fourth transistor. The second output current has a substantially zero temperature coefficient dependent on (i) a difference between an effective channel size of the first transistor and an effective channel size of the second transistor, and (ii) a difference between an effective channel size of the third transistor and an effective channel size of the fourth transistor.

Abstract: Variable bit size run length encoding (“RLE”) is used to encode uninterrupted runs of adjacent first symbols and adjacent second symbols within a sequence that may represent an image. The symbols may be 1s and 0s. The bit size used to encode a run length for a current run is varied in dependence on the bit sized used or required to encode a run length of a previous run of the same symbol type. Further, an image to be encoded may be transformed into an image/bit sequence representing changes from line to line in the image. By so transforming the image, the correlation from run length to run length of like colors is increased, thereby improving the efficiency of the variable bit size RLE.

Abstract: A first set of display information is received at a device driver. The first set of display information indicates a portion of the video image to be displayed in a first window of a first monitor. An aspect ratio of the video image is determined based on the first set of display information. Based on the determined aspect ratio, the display driver determines a location on a second display device where the video image is to also be displayed.

Abstract: Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.

Abstract: A method and apparatus from removing image compression artifacts includes comparing a center pixel value with a perimeter pixel value to generate a compare pixel value. The compare pixel value is compared with a threshold value such that when the compare pixel value is below a threshold value, a count value is incremented and an accumulation value is accumulated. The method and apparatus includes repeating the comparison of perimeter pixel values with the center pixel values. The method and apparatus further includes if the count value has been incremented, generating an output center pixel value based on the quotient of the accumulation value divided by the count value as the center pixel value.

Abstract: The subject matter relates to a virtual stereoscopic camera for displaying 3D images. In one implementation, left and right perspectives of a source are captured by image capturing portions. The image capturing portions include an array of image capturing elements that are interspersed with an array of display elements in a display area. The image capturing elements are confined within limited portions of the display area and are separated by an offset distance. The captured left and right perspectives are synthesized so as to generate an image that is capable of being viewed in 3D.

Abstract: An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

Abstract: A video playback circuit receives flip call information and vertical synchronization information, and in response determines a pause mode and a playback mode. Flip call information, as is known in the art, provides an indication for flipping between a front buffer and a back buffer, in order to facilitate rendering into one buffer while rasterizing out of the other buffer. Vertical synchronization information describes the completion of rasterizing an image onto a display, and often occurs at periodic intervals, e.g., 60 Hz, 100 Hz. The video playback circuit further includes a pause/playback-based frame buffer pointer information generator. The pause/playback-based frame buffer pointer information generator generates unfiltered frame buffer pointer information when in the pause mode. Otherwise, the pause/playback-based frame buffer pointer information generator generates filtered frame buffer pointer information when in the playback mode.

Abstract: A digital pixel clock generation circuit receives image data and corresponding image presentation time information from at least one external image source. The digital pixel clock generation circuit includes an image presentation timing error determination circuit that produces desired pixel clock frequency control information, such as pixel output clock adjustment control information, based on a difference between an expected presentation time and an actual presentation image time information. A programmable digital waveform generation circuit is programmed based on the produced desired pixel clock frequency and has an input that is responsive to an independent clock source, that is independent from the clock source of the external image source. The programmable digital waveform generation circuit provides a digital representation of an independently generated desired pixel clock which is then output to a digital to analog converter (DAC).

Abstract: A method and apparatus provides context switching of logic in an integrated circuit using one or more test scan circuits that use test data during a test mode of operation of the integrated circuit to store and/or restore non-test data during normal operation of the integrated circuit. The integrated circuit includes context control logic operative to control the test scan circuit to at least one of: store and restore context state information contained in functional storage elements in response to detection of a request for a change in context during normal operation of the integrated circuit.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.