Abstract: A technique for determining a quality value for a subject block of encoded video is provided. Contributing blocks, of the same frame and/or different frames of the subject block, are determined by identifying blocks likely to be a part of the same moving object or background as the subject block. A spatial and/or temporal filter is then applied to the quality values of the contributing blocks and an initial quality value of the subject block. With a spatial filter, quality values for contributing blocks from the same frame are combined and used to modify the quality value of the subject block. With a spatial filter, a temporal characteristic quality value for contributing blocks of one or more other frames (such as the immediately previous frame) is determined and then combined with a quality value representative of the subject block.

Abstract: Techniques are provided herein for processing video data. The techniques include generating predicted macroblock coding modes for a set of macroblocks of a frame, assigning quantization parameters to the macroblocks based on the predicted macroblock coding modes, and encoding the set of macroblocks based on the quantization parameters.

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Abstract: An encoder encodes pixels representative of a picture in a multimedia stream, generates a first approximate signature based on approximate values of pixels in a reconstructed copy of the picture, and transmits the encoded pixels and the first approximate signature. A decoder receives a first packet including the encoded pixels and the first approximate signature, decodes the encoded pixels, and transmits a first signal in response to comparing the first approximate signature and a second approximate signature generated based on approximate values of the decoded pixels. If a corrupted packet is detected, the multimedia application requests an intra-coded picture in response to the first approximate signature differing from the second approximate signature. The second signal instructs the decoder to bypass requesting an intra-coded picture and to continue decoding received packets in response to the first approximate signature being equal to the second approximate signature.

Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

Abstract: Various audio encoders and methods of using the same are disclosed. In one aspect, an apparatus is provided that includes an audio encoder and an audio encoder mode selector. The audio encoder mode selector is operable to analyze video data and adjust an encoding mode of the audio encoder based on the analyzed video data.

Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.

Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.

Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.

Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.

Abstract: Briefly, methods and apparatus to provide image content to, and display image content on, variable refresh rate displays with reduced input lag. The methods and apparatus allow for image tearing, or the displaying of image content from more than one video frame, when the render rate of a provided video frame falls outside the display refresh rate range of a variable refresh rate display when the display is refreshing with a previous frame (e.g. the display is in active refresh), thus reducing the input lag of the content of the provided video frame. The methods and apparatus may also prevent image tearing when the render rate of provided video frames is within the display refresh rate range of a display.

Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Abstract: A display system includes a rendering device configured to couple to a display monitor. The rendering device includes a graphics processing unit (GPU) configured to render display images for a video stream to be displayed at the display monitor. The rendering device further includes a central processing unit (CPU) configured to obtain display parameters for the display monitor, the display parameters including data identifying a native color gamut, a native luminance range of the display monitor, and one or more backlighting characteristics of the display monitor, and to configure the GPU to render a display image of the video stream that is tone mapped to the native color gamut and the native luminance range and based on the one or more backlighting characteristics. The display monitor is configured to provide the display image for display without tone re-mapping the display image.

Abstract: A processing system filters blocks of a picture to minimize a size and error of the blocks prior to encoding. A pre-processing module of the processing system measures characteristics of a plurality of blocks and evaluates the effects of applying each of a plurality of filters to the blocks prior to encoding in order to predict an increase in compressibility of blocks having similar characteristics that are filtered with each filter before being encoded, with the least impact on quality. The pre-processing module trains models to predict a size and error of blocks filtered with each filter based on block characteristics. The pre-processing module uses the models to calculate a cost in terms of size and error of applying each filter to a given block having certain characteristics. The pre-processing module then applies to the block the filter that is predicted to result in the best cost.

Abstract: An encoder of a multimedia system encodes data representative of each image in a video stream to form a bitstream that is transmitted over a network to a decoder that decodes the bitstream and provides the decoded information to a multimedia application for display to the user. As consecutive images may have nearly identical pixel values, the multimedia system detects pixel value variations between consecutive images that are below a specified threshold to reduce active processing on such pictures, which includes, for example, encoding, decoding, and post-processing. The multimedia system either selectively encodes or selectively processes the current image that has pixel values that vary from an immediately preceding image within the specified threshold.

Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.

Abstract: A method and apparatus provides for enhanced processing of 3D graphics data such as image-based 3D graphics data. The image-based 3D graphics data may include data defining texture, bump, normals, displacement, etc for underlying objects. In one example, the method and apparatus compresses image-based 3D graphics data as one or more frames contained in one or more videos and decompresses the compressed 3D graphics data using video acceleration hardware provided by a GPU. In another example the method and apparatus may also selectively control caching of image-based 3D graphics data. Before so cached, the image-based 3D graphics data may be compressed as one or more frames contained in one or more videos using video acceleration hardware provided by the GPU to achieve efficient usage of cache space.