Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a sparsity of the feature maps and store the plurality of different feature maps in the memory.

Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.

Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.

Abstract: Power management in a computing device. A driver is registered with an operating system (OS) executing on the computing device to receive information about a position of a user interface control. If the user interface control is moved, the driver receives a notification of the user interface control position and determines a power management intervention based on the position. The driver transmits the power management intervention to power control circuitry which sets a power setting of the computing device based on the intervention.

Abstract: Systems, apparatuses, and methods for performing parallel histogram calculation with application to palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of pixel component value bits of a block of pixels. Then, the encoder selects a first number of the highest pixel count bins from the first histogram. Also, the encoder calculates a second histogram for a second portion of pixel component value bits of the block. The encoder selects a second number of the highest pixel count bins from the second histogram. A third histogram is calculated from the concatenation of bits assigned to the first and second number of bins, and the highest pixel count bins are selected from the third histogram. A palette table is derived based on these highest pixel count bins selected from the third histogram, and the block of pixels is encoded using the palette table.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.

Abstract: A method and apparatus obtains a source image having a plurality of source color gamut pixels in a source color gamut. The method and apparatus converts the plurality of source color gamut pixels to a plurality of corresponding target color gamut pixels using non-linear interpolation of a plurality of output pixel values from a reduced 3-D look-up table (LUT) for a target color gamut. The method and apparatus provides, for display, the plurality of target color gamut pixels (e.g., one or more pixels) on a target color gamut display.

Abstract: An oscillator circuit includes a first oscillator, a second oscillator, and a calibration circuit to calibrate the first and second oscillators. The first oscillator is supplied with a first supply voltage, and the second oscillator is supplied with a second supply voltage. The calibration includes setting a frequency control of the second oscillator at a target frequency. Then, a voltage control of the second supply voltage is adjusted incrementally until a first control value is identified at which a second oscillator output frequency matches the target frequency. Then, a voltage control of the first supply voltage is set to the first control value. Then, the voltage control for the first supply voltage is adjusted incrementally until a second control value is identified at which a first oscillator output frequency is as close to the second oscillator output frequency as is achievable, but does not exceed it.

Abstract: Systems, apparatuses, and methods for implementing a single-stream foveal display transport are disclosed. A system includes a transmitter sending an image over a display transport as a sequence of equi-sized rectangles to a receiver coupled to a display. The receiver then scales up the rectangles with different scale factors to cover display areas of different sizes. The pixel density within a rectangular region is uniform and scaling factors can take on integer or non-integer values. The rectilinear grid arrangement of the image results in simplified scaling operations for the display. In another scenario, the image is transmitted as a set of horizontal bands of equal size. Within each band, the same horizontal amount of transmitted pixels are redistributed across multiple rectangular regions of varied scales. The display stream includes embedded information and the horizontal and/or vertical distribution and scaling of rectangular regions, which can be adjusted for each transmitted image.

Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.

Abstract: Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.

Abstract: A single source image encoder encodes more than one display stream, such as multiple display streams each for a different display or multiple display streams for the same display, using multiple indexed color history (ICH) buffers. As applied to a DSC encoder, the same DSC encoder is used to encode more than one DSC compliant display stream. Multiple encoded display bitstreams are output as multiple display data streams to a plurality of displays. Such a configuration can significantly reduce the area cost of an integrated circuit that employs an image encoder since additional encoders are eliminated.

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

Abstract: A computing device and method controls power consumption of a graphics processing unit in the computing device by the GPU determining an allocated power for the USB device connected through a USB port, such as a USB-C port. The GPU issues allocated power information for the external USB device to cause the allocated power to be provided to the USB device and includes issuing allocated power information to a power delivery (PD) controller that is connected to a USB port. In some implementations, the GPU shifts at least a portion of the allocated power from the USB device back to the GPU in response to a usage change event associated with the USB device for improving GPU performance. The usage change event can be a disconnect event of the USB device, a power renegotiation event between the USB device and the GPU, or any other suitable usage change event.

Abstract: Systems, apparatuses, and methods for calculating multi-pass histograms for palette table derivation include an encoder that calculates a first histogram for a first portion of most significant bits (MSBs) of pixel component values of a block of an image or video frame. Then, the encoder selects a given number of the highest pixel count bins from the first histogram. The encoder then increases the granularity of these selected highest pixel count bins by evaluating one or more additional bits from the pixel component values. A second histogram is calculated for the concatenation of the original first portion MSBs from the highest pixel count bins and the one or more additional bits, and the highest pixel count bins are selected from the second histogram. A palette table is derived based on these highest pixel count bins selected from the second histogram, and the block is encoded using the palette table.

Abstract: Systems, apparatuses, and methods for reducing latency for wireless virtual and augmented reality applications are disclosed. A virtual reality (VR) or augmented reality (AR) system includes a transmitter rendering, encoding, and sending video frames to a receiver coupled to a head-mounted display (HMD). In one scenario, rather than waiting until the entire frame is encoded before sending the frame to the receiver, the transmitter sends an encoded left-eye portion to the receiver while the right-eye portion is being encoded. In another scenario, the frame is partitioned into a plurality of slices, and each slice is encoded and then sent to the receiver while the next slice is being encoded. In a further scenario, each slice is being encoded while the next slice is being rendered. In a still further scenario, each slice is prepared for presentation by the receiver while the next slice is being decoded by the receiver.

Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.

Abstract: Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.

Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.