Patents Assigned to ATI Technologies
  • Efficient quantization parameter prediction method for low latency video coding
    Patent number: 10924739
    Abstract: Systems, apparatuses, and methods for calculating a quantization parameter (QP) for encoding video frames to meet a given bit budget are disclosed. Control logic coupled to an encoder calculates a complexity indicator that represents a level of difficulty in encoding a previous video frame. The complexity indicator is based at least in part on a first parameter associated with the previous video frame and corresponds to one or more of a variance, an intra-prediction factor, and an inter-to-intra ratio. The complexity indicator is then used by the control logic to calculate a preferred QP to use to encode the current video frame to meet a given bit budget. By using the preferred QP generated based on the complexity indicator, the encoder is able to make fewer QP adjustments during the frame. This helps to improve the visual quality of the resulting encoded video bitstream.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 16, 2021
    Assignee: ATI Technologies ULC
    Inventors: Dennis Lew, Jiao Wang, Lei Zhang, Edward A. Harold
  • High density cross link die with polymer routing layer
    Patent number: 10923430
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: February 16, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Chun-Hung Lin, Rahul Agarwal, Milind Bhagavat, Fei Guo
  • Variable latency request arbitration
    Patent number: 10915359
    Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 9, 2021
    Assignee: ATI Technologies ULC
    Inventors: Jimshed B. Mirza, Qian Ma, Leon King Nok Lai
  • Multiple symbol decoder
    Patent number: 10917110
    Abstract: An electronic device for decompressing compressed data includes a decoding subsystem having a symbol decoder and a second symbol resolver with a number of local symbol decoders and a symbol selector. The symbol decoder decodes a first symbol from a first code for which a symbol is available in a block of the compressed data and communicates a length of the code to the second symbol resolver. Each local symbol decoder, substantially in parallel with the decoding of the first symbol in the symbol decoder, decodes a respective symbol from a first code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver selects, as a second symbol, based on the length received from the symbol decoder, one of the respective symbols from the local symbol decoders. The decoding subsystem then provides the first and second symbols.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: February 9, 2021
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: Vinay Patel
  • Data transmission using flippable cable
    Patent number: 10909060
    Abstract: A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 2, 2021
    Assignee: ATI Technologies ULC
    Inventor: James Hunkins
  • Providing copies of input-output memory management unit registers to guest operating systems
    Patent number: 10909053
    Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: February 2, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Maggie Chan, Philip Ng, Paul Blinzer
  • METHOD AND SYSTEM FOR IMPROVED VISIBILITY IN BLENDED LAYERS FOR HIGH DYNAMIC RANGE DISPLAYS
    Publication number: 20210027437
    Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.
    Type: Application
    Filed: October 13, 2020
    Publication date: January 28, 2021
    Applicant: ATI Technologies ULC
    Inventors: Jie Zhou, David I. J. Glen
  • METHOD AND APPARATUS FOR DETERMINING LINK BIFURCATION AVAILABILITY
    Publication number: 20210026797
    Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 28, 2021
    Applicant: ATI Technologies ULC
    Inventors: Natale Barbiero, Gordon Caruk
  • Single display pipe multi-view frame composer method and apparatus
    Patent number: 10904507
    Abstract: A method and apparatus for providing multi-view composed frames uses a single display pipe mechanism. The single display pipe includes, in one example, a memory requestor that fetches multi-view data from a frame buffer using a plurality of viewports. The single display pipe may also include a multi-view packer. Each viewport of the single display pipe has access to a frame buffer holding multi-view frame data, and may be configured to have access to different areas of the frame buffer. In this fashion the single display pipe may fetch data representing more than one view of a multi-view frame. Additionally, the multi-view packer combines the data fetched from one or more of the viewports to form a multi-view frame to be supplied for display.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 26, 2021
    Assignee: ATI Technologies ULC
    Inventor: Dennis Au
  • Method and apparatus for data scrambling
    Patent number: 10895901
    Abstract: A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 19, 2021
    Assignees: ADVANCED MICRO DEVICES INC., ATI TECHNOLOGIES ULC
    Inventors: Yanfeng Wang, Michael J. Tresidder, Kevin M. Lepak, Larry David Hewitt, Noah Beck
  • Frame refresh synchronization with synchronization boundary
    Patent number: 10891915
    Abstract: A GPU is generally configured to detect changes in the rate of frame generation that can result from, for example, changes in the complexity of the frames being generated. In response to detecting the change in the rate of frame generation, the GPU identifies a corresponding change in the refresh rate that would be required to fully synchronize the refresh rate with the rate of frame generation. If the change in the refresh rate falls outside the boundaries of a specified or dynamically generated window, the GPU limits the change in refresh rate to the corresponding boundary.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 12, 2021
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Anthony W L Koo, Aric Cyr, Syed Athar Hussain
  • FIRMWARE ANTI-ROLLBACK
    Publication number: 20210004466
    Abstract: A platform security processor is booted and reads a set of write-once memory bits to obtain a minimum security patch level (SPL). The security processor then verifies that a table SPL for a firmware security table is greater than or equal to the minimum SPL. The firmware security table includes a plurality of firmware identifiers for firmware code modules, and a plurality of check SPL values each associated with respective one of the firmware identifiers. The security processor verifies SPL values in a plurality of firmware code modules by, for each firmware code module, accessing the module to obtain its firmware SPL value and check if the respective firmware SPL value is equal to or greater than a respective check SPL value in the firmware security table.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 7, 2021
    Applicant: ATI Technologies ULC
    Inventors: Kathirkamanathan Nadarajah, Benedict Chien
  • MULTI-TIERED LOW POWER STATES
    Publication number: 20200409448
    Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou
  • Application profiling for power-performance management
    Patent number: 10877547
    Abstract: A processing apparatus is provided which includes memory configured to store hardware parameter settings for each of a plurality of applications. The processing apparatus also includes a processor in communication with the memory configured to store, in the memory, the hardware parameter settings, identify one of the plurality of applications as a currently executing application and control an operation of hardware by tuning a plurality of hardware parameters according to the stored hardware parameter settings for the identified application.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: December 29, 2020
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Shahriar Pezeshgi, Jun Huang, Mohammad Hamed Mousazadeh, Alexander S. Duenas
  • Method and system for partial wavefront merger
    Patent number: 10877926
    Abstract: A method and system for partial wavefront merger is described. Vector processing machines employ the partial wavefront merger to merge partial wavefronts into one or more wavefronts. The system includes a partial wavefront manager and unified registers. The partial wavefront manager detects wavefronts in different single-instruction-multiple-data (“SIMD”) units which contain inactive work items and active work items (hereinafter referred to as “partial wavefronts”), moves the partial wavefronts into one or more SIMD unit(s) and merges the partial wavefronts into one or more wavefront(s). The unified register allows each active work item in the one or more merged wavefront(s) to access the previously allocated registers in the originating SIMD units. Consequently, the contents of the unified registers do not have to be copied to the SIMD unit(s) executing the one or merged wavefront(s).
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 29, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Yunpeng Zhu, Jimshed Mirza
  • Low latency wireless Virtual Reality systems and methods
    Patent number: 10880587
    Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 29, 2020
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: Lei Zhang, Gabor Sines, Khaled Mammou, David Glen, Layla A. Mah, Rajabali M. Koduri, Bruce Montag
  • Deskewing method for a physical layer interface on a multi-chip module
    Patent number: 10873445
    Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 22, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
  • Three dimensional (3-D) look up table (LUT) used for gamut mapping in floating point format
    Patent number: 10867580
    Abstract: A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: December 15, 2020
    Assignee: ATI TECHNOLOGIES ULC
    Inventor: Yuxin Chen
  • Inter device data exchange via external bus by utilizing communication port
    Patent number: 10866917
    Abstract: The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 15, 2020
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Serguei Sagalovitch, Ilya Panfilov
  • Steering tag support in virtualized environments
    Patent number: 10866895
    Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 15, 2020
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Philip Ng, Nippon Harshadk Raval, Francisco L. Duran