Patents Assigned to ATI Technologies
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Publication number: 20210026797Abstract: A method and apparatus for determining link bifurcation availability implemented in a computer system includes assigning, by a controller, lanes that include links for one or more components connected in accordance with a current known configuration. The controller transmits ordered sets including the assignments to the one or more components which are received by the one or more components. The one or more components respond with a first link to the controller. Based upon the links received by the controller not meeting the current known configuration, the controller issues an interrupt and is reconfigured.Type: ApplicationFiled: July 24, 2019Publication date: January 28, 2021Applicant: ATI Technologies ULCInventors: Natale Barbiero, Gordon Caruk
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Publication number: 20210027437Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Applicant: ATI Technologies ULCInventors: Jie Zhou, David I. J. Glen
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Patent number: 10904507Abstract: A method and apparatus for providing multi-view composed frames uses a single display pipe mechanism. The single display pipe includes, in one example, a memory requestor that fetches multi-view data from a frame buffer using a plurality of viewports. The single display pipe may also include a multi-view packer. Each viewport of the single display pipe has access to a frame buffer holding multi-view frame data, and may be configured to have access to different areas of the frame buffer. In this fashion the single display pipe may fetch data representing more than one view of a multi-view frame. Additionally, the multi-view packer combines the data fetched from one or more of the viewports to form a multi-view frame to be supplied for display.Type: GrantFiled: October 22, 2018Date of Patent: January 26, 2021Assignee: ATI Technologies ULCInventor: Dennis Au
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Publication number: 20210004466Abstract: A platform security processor is booted and reads a set of write-once memory bits to obtain a minimum security patch level (SPL). The security processor then verifies that a table SPL for a firmware security table is greater than or equal to the minimum SPL. The firmware security table includes a plurality of firmware identifiers for firmware code modules, and a plurality of check SPL values each associated with respective one of the firmware identifiers. The security processor verifies SPL values in a plurality of firmware code modules by, for each firmware code module, accessing the module to obtain its firmware SPL value and check if the respective firmware SPL value is equal to or greater than a respective check SPL value in the firmware security table.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Applicant: ATI Technologies ULCInventors: Kathirkamanathan Nadarajah, Benedict Chien
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Publication number: 20200409448Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou
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Patent number: 10877926Abstract: A method and system for partial wavefront merger is described. Vector processing machines employ the partial wavefront merger to merge partial wavefronts into one or more wavefronts. The system includes a partial wavefront manager and unified registers. The partial wavefront manager detects wavefronts in different single-instruction-multiple-data (“SIMD”) units which contain inactive work items and active work items (hereinafter referred to as “partial wavefronts”), moves the partial wavefronts into one or more SIMD unit(s) and merges the partial wavefronts into one or more wavefront(s). The unified register allows each active work item in the one or more merged wavefront(s) to access the previously allocated registers in the originating SIMD units. Consequently, the contents of the unified registers do not have to be copied to the SIMD unit(s) executing the one or merged wavefront(s).Type: GrantFiled: July 23, 2018Date of Patent: December 29, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Yunpeng Zhu, Jimshed Mirza
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Patent number: 10873445Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.Type: GrantFiled: December 10, 2019Date of Patent: December 22, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Varun Gupta, Milam Paraschou, Gerald R. Talbot, Gurunath Dollin, Damon Tohidi, Eric Ian Carpenter, Chad S. Gallun, Jeffrey Cooper, Hanwoo Cho, Thomas H. Likens, III, Scott F. Dow, Michael J. Tresidder
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Publication number: 20200382801Abstract: A video keying processing device is provided which comprises memory configured to store data and a processor configured to determine, which pixel portions, in a YUV color space of a first video comprising a foreground object and a background color, represent the foreground object and the background color of the first video. The processor is also configured to, for each pixel portion of the first video determined to represent the foreground object and the background color, convert YUV values of the pixel portion to red-green-blue (RGB) color component value and determine a blended display value for each RGB color component of the pixel portion based on a blending factor. The processor is also configured to generate a composite video for display using the blended display values of each pixel portion determined to represent the foreground object and the background color.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Applicant: ATI Technologies ULCInventors: Yubao Zheng, Gabor Sines
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Publication number: 20200379544Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 10853263Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.Type: GrantFiled: July 23, 2019Date of Patent: December 1, 2020Assignee: ATI Technologies ULCInventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, William Lloyd Atkinson
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Patent number: 10855222Abstract: A clock synthesizer has integrated voltage droop detection and clock stretching. An oscillator of the clock synthesizer receives a control current from a digital to analog converter and generates an oscillator output signal. A droop detector and clock stretching circuit responds to a voltage droop of a supply voltage supplying circuits coupled to the oscillator output signal, to cause a portion of the oscillator control current to be diverted from the oscillator to thereby cause the oscillator to reduce the first frequency. The diversion can be accomplished through shunt circuits or a current mirror circuit.Type: GrantFiled: June 29, 2018Date of Patent: December 1, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Dirk J. Robinson, Andy Huei Chu, Yan Sun, Saket Sham Doshi
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Patent number: 10848137Abstract: A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.Type: GrantFiled: May 8, 2019Date of Patent: November 24, 2020Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Mikhail Rodionov, Stephen Victor Kosonocky, Joyce Cheuk Wai Wong
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Patent number: 10848772Abstract: Described is a system and method for dynamically changing encode quality at a block level based on runtime pre-encoding analysis of content in a video stream. A video encoder continuously analyzes the content during runtime, and collects statistics and/or characteristics of the content before encoding it. This classifies the block among pre-defined categories of content, where every category has its own compression parameters.Type: GrantFiled: September 28, 2018Date of Patent: November 24, 2020Assignee: ATI Technologies ULCInventors: Boris Ivanovic, Mehdi Saeedi
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Patent number: 10841156Abstract: Systems, apparatuses, and methods for remotely adjusting performance and power parameters of a computing device are disclosed. A computing system includes a first computing device connected to a second (remote) computing device. The user uses the second computing device to monitor and adjust parameters, such as a fan speed for a GPU on a video graphics card in the first computing device, while the first computing device executes a parallel data application such as a video game. Additionally, the user uses the second computing device to manage video recorder operations. By using the second computing device to send commands to a graphics driver and a video recorder application, the first computing device's display monitor does not display a user interface during execution of the video game. No video rendering is performed by the video graphics card of the first computing device to generate and control the user interface.Type: GrantFiled: April 27, 2018Date of Patent: November 17, 2020Assignee: ATI Technologies ULCInventors: Amir Alam, Patrick Pak Kin Fok, Le Zhang, Ilia Blank
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Publication number: 20200358447Abstract: A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Mikhail Rodionov, Stephen Victor Kosonocky, Joyce Cheuk Wai Wong
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Publication number: 20200357093Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Guennadi Riguer, Brian K. Bennett
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Patent number: 10832389Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.Type: GrantFiled: December 13, 2018Date of Patent: November 10, 2020Assignee: ATI Technologies ULCInventors: Jie Zhou, David I. J. Glen
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Patent number: 10796400Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: October 14, 2019Date of Patent: October 6, 2020Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20200314422Abstract: A technique for determining a quality value for a subject block of encoded video is provided. Contributing blocks, of the same frame and/or different frames of the subject block, are determined by identifying blocks likely to be a part of the same moving object or background as the subject block. A spatial and/or temporal filter is then applied to the quality values of the contributing blocks and an initial quality value of the subject block. With a spatial filter, quality values for contributing blocks from the same frame are combined and used to modify the quality value of the subject block. With a spatial filter, a temporal characteristic quality value for contributing blocks of one or more other frames (such as the immediately previous frame) is determined and then combined with a quality value representative of the subject block.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: ATI Technologies ULCInventors: Mehdi Saeedi, Boris Ivanovic
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Publication number: 20200296393Abstract: Techniques are provided herein for processing video data. The techniques include generating predicted macroblock coding modes for a set of macroblocks of a frame, assigning quantization parameters to the macroblocks based on the predicted macroblock coding modes, and encoding the set of macroblocks based on the quantization parameters.Type: ApplicationFiled: March 13, 2020Publication date: September 17, 2020Applicant: ATI Technologies ULCInventors: Mehdi Saeedi, Boris Ivanovic