Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: In an embodiment, a bias generator circuit comprises a first circuit and a second circuit. The first circuit includes a first input coupled to a voltage source and a first output that provides a first output current having a substantially non-zero temperature coefficient. The first circuit comprises a first transistor and a second transistor. The second circuit includes a second input that receives the first output current from the first circuit and a second output that provides a second output current. The second circuit comprises a third transistor and a fourth transistor. The second output current has a substantially zero temperature coefficient dependent on (i) a difference between an effective channel size of the first transistor and an effective channel size of the second transistor, and (ii) a difference between an effective channel size of the third transistor and an effective channel size of the fourth transistor.

Abstract: Variable bit size run length encoding (“RLE”) is used to encode uninterrupted runs of adjacent first symbols and adjacent second symbols within a sequence that may represent an image. The symbols may be 1s and 0s. The bit size used to encode a run length for a current run is varied in dependence on the bit sized used or required to encode a run length of a previous run of the same symbol type. Further, an image to be encoded may be transformed into an image/bit sequence representing changes from line to line in the image. By so transforming the image, the correlation from run length to run length of like colors is increased, thereby improving the efficiency of the variable bit size RLE.

Abstract: A video graphics module capable of blending multiple image layers includes a plurality of video graphic pipelines, each of which is operable to process a corresponding image layer. One of the video graphic pipelines processes a foremost image layer. For example, the foremost image layer may be a hardware cursor. The video graphics module also includes a blending module that is operably coupled to the plurality of video graphic pipelines. The blending module blends, in accordance with a blending convention (e.g., AND/Exclusive OR blending and/or alpha blending), the corresponding image layers of each pipeline in a predetermined blending order to produce an output image. The blending module blends the foremost image layer such that it appears in a foremost position with respect to the other image layers.

Abstract: A first set of display information is received at a device driver. The first set of display information indicates a portion of the video image to be displayed in a first window of a first monitor. An aspect ratio of the video image is determined based on the first set of display information. Based on the determined aspect ratio, the display driver determines a location on a second display device where the video image is to also be displayed.

Abstract: Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.

Abstract: An audio/video separator provides a high-performance and cost-effective solution to analog TV reception with only one A/D converter and a minimum of analog IF components. The apparatus may operate on a digitized TV signal and, when integrated with a digital video processor, process video signals while separating audio signals. The resultant audio and video signals may be considered to have excellent signal quality due to highly optimized demodulation architecture and digital signal processing techniques on both audio and video data paths.

Abstract: A method and apparatus from removing image compression artifacts includes comparing a center pixel value with a perimeter pixel value to generate a compare pixel value. The compare pixel value is compared with a threshold value such that when the compare pixel value is below a threshold value, a count value is incremented and an accumulation value is accumulated. The method and apparatus includes repeating the comparison of perimeter pixel values with the center pixel values. The method and apparatus further includes if the count value has been incremented, generating an output center pixel value based on the quotient of the accumulation value divided by the count value as the center pixel value.

Abstract: The subject matter relates to a virtual stereoscopic camera for displaying 3D images. In one implementation, left and right perspectives of a source are captured by image capturing portions. The image capturing portions include an array of image capturing elements that are interspersed with an array of display elements in a display area. The image capturing elements are confined within limited portions of the display area and are separated by an offset distance. The captured left and right perspectives are synthesized so as to generate an image that is capable of being viewed in 3D.

Abstract: An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

Abstract: A video playback circuit receives flip call information and vertical synchronization information, and in response determines a pause mode and a playback mode. Flip call information, as is known in the art, provides an indication for flipping between a front buffer and a back buffer, in order to facilitate rendering into one buffer while rasterizing out of the other buffer. Vertical synchronization information describes the completion of rasterizing an image onto a display, and often occurs at periodic intervals, e.g., 60 Hz, 100 Hz. The video playback circuit further includes a pause/playback-based frame buffer pointer information generator. The pause/playback-based frame buffer pointer information generator generates unfiltered frame buffer pointer information when in the pause mode. Otherwise, the pause/playback-based frame buffer pointer information generator generates filtered frame buffer pointer information when in the playback mode.

Abstract: A digital pixel clock generation circuit receives image data and corresponding image presentation time information from at least one external image source. The digital pixel clock generation circuit includes an image presentation timing error determination circuit that produces desired pixel clock frequency control information, such as pixel output clock adjustment control information, based on a difference between an expected presentation time and an actual presentation image time information. A programmable digital waveform generation circuit is programmed based on the produced desired pixel clock frequency and has an input that is responsive to an independent clock source, that is independent from the clock source of the external image source. The programmable digital waveform generation circuit provides a digital representation of an independently generated desired pixel clock which is then output to a digital to analog converter (DAC).

Abstract: A method and apparatus provides context switching of logic in an integrated circuit using one or more test scan circuits that use test data during a test mode of operation of the integrated circuit to store and/or restore non-test data during normal operation of the integrated circuit. The integrated circuit includes context control logic operative to control the test scan circuit to at least one of: store and restore context state information contained in functional storage elements in response to detection of a request for a change in context during normal operation of the integrated circuit.

Abstract: In accordance with a specific aspect of the present disclosure, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized and written to an output buffer location.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed.

Abstract: A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fixed, relatively small page size. The page table is broken into fragments made up of pages that are contiguous in physical address space and logical address space and have similar attributes. Fragments in logical address space begin on known boundaries such that the boundary indicates both a starting address of a fragment and the size of the fragment. Corresponding fragments in physical address space can begin anywhere, thus making the process transparent to physical memory. A fragment field in a page table entry conveys both fragment size and boundary information.

Abstract: Method for automatic image reorientation is disclosed. In an embodiment, the method includes reorienting a displayed image in response to a change in relative orientation of a viewer image with respect to a reference image. The reorientation is performed to compensate, at least partially, for the change in relative orientation of the viewer image.