Abstract: A circuit and a method of operation to reduce dynamic and static power dissipation in the circuit are disclosed. The circuit is multi-threshold, voltage-biased and includes a p-channel field effect transistor (FET) and an n-channel FET. A source terminal of the p-channel FET interconnects to a higher-voltage rail of a power supply and a source terminal of the n-channel FET interconnects to a lower-voltage rail of the power supply. At least one of the FETs includes a back contact. The circuit may be operated by applying a fixed bias voltage to the back contact. The fixed bias voltage is independent of the power supply voltage which may be varied. In a normal state, the supply voltage is adjusted to decrease dynamic power consumption. In a low power state, the supply voltage is further adjusted to limit leakage current. The circuit may optionally include a second fixed biasing voltage source so that both FETs are biased.

Abstract: One of a video source device and a video sink device may: (a) deactivate a video processing function at the one device and send a command for causing the other of the video source device and the video sink device to activate the video processing function; (b) activate the video processing function at the one device and send a command for causing the other device to deactivate the video processing function; and (c) based on user input indicating whether (a) or (b) resulted in a preferred video image, effect (a) or (b). The one device may receive an indication of video processing functions of which the other device is capable, such that (a), (b) and (c) may be performed for each indicated video processing function of which the one device is also capable. A user interface including at least one selectable control for indicating whether a video image resulting from (a) or (b) is preferred may be displayed.

Abstract: A method for selecting an antenna direction setting for optimum signal reception prior to channel equalization provides a set of metrics, referred to as channel quality metrics (CQM), that characterize the quality of the received signal for a given antenna setting and a generic algorithm that uses these metrics to select the antenna setting for an optimum reception. This invention utilizes five main CQMs: a Signal Strength Metric (SSM), a minimum mean squared error of a decision feedback equalizer (MMSE (DFE)) channel quality metric, a MMSE for a linear equalizer (MMSE(LE)) channel quality metric, a Spectral Flatness Metric (SFM) and an interference degradation metric (IDM).

Abstract: Disclosed are methods and apparatus for accomplishing the fetching or sampling of channels of pixels or texels such as neighboring pixels or texels or non-neighboring pixels or texels in a simultaneous operation in order to achieve optimization of the performance of a texture pipeline. In particular, logic is disclosed including selector logic configured to retrieve data including a plurality of channels from each of a plurality of pixels or texels and operable to select one channel from the plurality of channels of the data from each of the pixels or texels. The logic also includes combination logic configured to combine two or more of the selected channels into a single vector, such as an RGBA vector representing the color.

Abstract: In a digital communications receiver configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of data bits, a method of processing the received signal includes adjusting a magnitude, filtering, and applying cyclic prefix restoration, to the received signal to produce a second signal, converting the second signal from time domain to frequency domain to produce a frequency domain signal, and determining a first quantity of values representing a first portion of the symbols by evaluating a relationship of channel values representing characteristics of the communications channel and a second quantity of values representing a portion of the frequency domain signal, the first quantity being smaller than the second quantity.

Abstract: To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms.

Abstract: A method includes reducing power of a first graphics processor by disabling or not using its rendering engine and leaving a display engine of the same first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display. A display frame is rendered by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state, such as a non-rendering state. The rendered frame is stored in a corresponding second frame buffer of the second graphics processor, such as a local frame buffer and copied from the second frame buffer to the first frame buffer. The copied frame in the first frame buffer is then displayed on a display while the rendering engine of the first graphics processor is in the reduced power state.

Abstract: At one of a video source device and a video sink device, an indication of video processing capabilities of the other of the video source device and said video sink device is received. Based upon the indication and an indication of video processing capabilities of the one device, one of a plurality of video processing algorithms is selected for execution by the one device. The selecting may be based upon a set of precedence rules. Categories of video processing may for example include scan-rate conversion, interlacing, de-interlacing, de-noise, scaling, color correction, contrast correction and detail enhancement.

Abstract: In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing.

Abstract: An electrical connector, such as a circuit board connector, includes a housing having therein a divided multi-connector element. The electrical connector is adapted to electrically connect with a substrate, such as a circuit board. The divided multi-connector element includes a divided electrical contact configuration that includes a first group or subassembly of electrical contacts physically separate from an adjacent and second group or subassembly of contacts. The first group of electrical contacts and second group of electrical contacts each include a row of lower contacts and upper contacts. The second group of electrical contacts has an identical but mirrored configuration as the first group of electrical contacts.

Abstract: A method for deinterlacing video includes constructing a temporary frame of deinterlaced video based on a first (i.e., current) field of interlaced video, wherein the temporary frame includes pixels in lines of the temporary frame associated with the first field of interlaced video, placeholder pixels in identified areas of motion in lines of the frame associated with a missing field of interlaced video, and pixels from an opposite field of polarity of interlaced video in areas without motion. The method further includes replacing the placeholder pixels in the identified areas of motion with pixels interpolated using an edge direction interpolation scheme based on pixels in the first field of interlaced video, resulting in a reconstructed frame. In one example, a motion adaptive interpolator may construct the temporary frame, and an edge directional interpolator may generate the reconstructed/deinterlaced the frame.

Abstract: Apparatus and methods relate to applications with references to profiles, wherein the profiles have parameter information that corresponds to device graphical user interface options. Profiles may be associated with hardware operations of the device, such as image, video, or audio en/decoding, and the parameter information corresponds to the capabilities and specifications of a hardware device. Corresponding systems for creating applications with at least one profile reference are also described.

Abstract: A wide gamut RGB digital display, such as an LCD display, digital television, printer, or any other suitable display, includes wide color gamut configuration message control logic that is operative to indicate, to an image source provider, wide gamut RGB indication information and wide color gamut format definition information that indicates that wide gamut RGB color data is to be received by the wide gamut RGB digital display. The wide gamut configuration message control logic is also operatively responsive to wide gamut confirmation information that is received from the image source provider. The wide gamut RGB digital display also includes logic that is operative to display received wide gamut RGB color data that was received in response to the wide gamut RGB indication information and the format definition information.

Abstract: An apparatus is operative to output display data for displaying a first application window and a second application window, wherein each application window is associated with an active application. The apparatus attaches the first application window with a first grid section using a grid management system, and based on user input associated with the second application window, performs a grid-based operation, such as swapping, splitting, or sharing. A method is also described that includes one or more of a grid-based swapping operation, a grid-based splitting operation, and a gird-based sharing operation.

Abstract: The embodiments of the present invention are a method and apparatus to perform anti-aliasing using multi-sampling on a non-power-of-two pixel grid. Using the present invention with 6 sample multisampling gives the same visual antialiasing quality as 8 samples using a prior art technique but uses less memory. A non-power-of-two equally spaced sample from a conventional grid of size N×N, where N is 12 can be chosen using the present invention. A scan conversion to determine the set of pixels covered by a polygon is performed in two parts. According to one embodiment, the present invention can multiply and divide by “N” in order to multisample an image using samples per pixel chosen from a N×N sub-sample grid, where “N” is not necessarily a power of 2. The present invention performs the divide by “N” step, where the step is achieved using a quick divide by 3 or 12 technique.

Abstract: An austenitic stainless steel having low nickel and molybdenum and exhibiting comparable corrosion resistance and formability properties to higher nickel and molybdenum alloys comprises, in weight %, up to 0.20 C, 2.0-9.0 Mn, up to 2.0 Si, 16.0-23.0 Cr, 1.0-5.0 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.1-0.35 N, up to 4.0 W, up to 0.01 B, up to 1.0 Co, iron and impurities, the steel having a ferrite number of less than 10 and a MD30 value of less than 20° C.

Abstract: A nucleated casting apparatus including an atomizing nozzle configured to produce a droplet spray of a metallic material, a mold configured to receive the droplet spray and form a preform therein, and a gas injector which can limit, and possibly prevent, overspray from accumulating on the mold. The gas injector can be configured to produce a gas flow which can impinge on the droplet spray to redirect at least a portion of the droplet spray away from a side wall of the mold. In various embodiments, the droplet spray may be directed by the atomizing nozzle in a generally downward direction and the gas flow may be directed in a generally upward direction such that the gas flow circumscribes the perimeter of the mold.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

Abstract: The present invention is directed to a method, computer program product, and system for processing memory access requests. The method includes the following features. First, page table entries of a page table are organized into at least one fragment that maps logical memory to at least one of logical memory or physical memory. The at least one fragment has a fragment size and an alignment boundary. Then, a subset of the page table entries stored in one of a plurality of cache banks is accessed to determine a mapping between a first logical memory address and at least one of a second logical memory address or a physical memory address. Each cache bank is configured to store at least one page table entry corresponding to a fragment of a predetermined set of fragment sizes and a predetermined alignment boundary.