Abstract: A nickel-base alloy having favorable toughness and thermal fatigue resistance comprises, in weight percentages based on total alloy weight: 9 to 20 chromium; 25 to 35 iron; 1 to 3 molybdenum; 3.0 to 5.5 niobium; 0.2 to 2.0 aluminum; 0.3 to 3.0 titanium; less than 0.10 carbon; no more than 0.01 boron; nickel; and incidental impurities. Also disclosed are die casting dies, other tooling, and other articles of manufacture made from or comprising the nickel-base alloy.

Abstract: To detect at least one of a copy protection indicator and a redistribution control indicator in an analog video signal, the video format of the analog video signal is determined, e.g., by detecting the horizontal frequency and vertical frequency of the signal. Based at least on the determined video format, a region of the analog video signal that may contain the indicator is identified. The region may for example be one or more video lines in a vertical blanking interval. The region is examined until the indicator is detected. The indicator is confirmed, e.g., by re-detecting one or more occurrences of the same indicator value(s) later in the video signal. Once confirmed, the indicated copy protection and/or redistribution control may be effected by limiting either or both of copying and redistribution of the analog video signal. The indicator may for example be Copy Generation Management System Analog plus Redistribution Control (CGMS-A+RC) information.

Abstract: A configurable multiple inlet thermal management device, such as an air-mover or passive heat sink, for electronic devices. The thermal management device is arranged on a computing device or on a component of a computing device or similar, such as an expansion module or alike, so that incoming air flow decreases the temperature of the heat producing components. In order to provide best possible air flow the air-mover comprises blade design that pressurizes the air flow from at least one side of the air-mover component. The air-mover includes removable covers for providing the openings required for intake air from the desired direction and for providing a fan wind. Depending on the application the openings may be permanently opened or closed. The intake air flow is then directed in form of fan wind towards the heat producing elements.

Abstract: A method and apparatus stores data representing a non 1:1 memory access interleaving ratio for accessing a plurality of memories. The method and apparatus interleaves memory accesses to at least either a first memory that is accessible via a first (and associated memory) bus having first characteristics or a second memory accessible via a second bus having different characteristics, based on the data representing the non 1:1 interleaving memory access ratio.

Abstract: A circuit substrate includes an outer plated through hole structure and an inner plated through hole structure located within the outer plated through hole structure. In one example, the circuit substrate includes a core and an outer plated through hole structure having a first metal layer configured over the core to form an outer plated through hole. The circuit substrate also includes an inner plated through hole structure located within the outer plated through hole structure having a second metal layer positioned inside of the outer plated through hole with an insulation layer interposed between the first and second metal layers. Methods for making such a circuit substrate are also described.

Abstract: A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

Abstract: The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30, 2004 and entitled SIMD PROCESSOR AND ADDRESSING METHOD.

Abstract: An apparatus for melting an electrically conductive metallic material includes a vacuum chamber and a hearth disposed in the vacuum chamber. At least one wire-discharge ion plasma electron emitter is disposed in or adjacent the vacuum chamber and is positioned to direct a wide-area field of electrons into the vacuum chamber, wherein the wide-area electron field has sufficient energy to heat the electrically conductive metallic material to its melting temperature. The apparatus may further include at least one of a mold and an atomizing apparatus which is in communication with the vacuum chamber and is positioned to receive molten material from the hearth.

Abstract: A method of reducing the formation of electrically resistive scale on a an article comprising a silicon-containing ferritic stainless subjected to oxidizing conditions in service includes, prior to placing the article in service, subjecting the article to conditions under which silica, which includes silicon derived from the steel, forms on a surface of the steel. Optionally, at least a portion of the silica is removed from the surface to placing the article in service. A ferritic stainless steel alloy having a reduced tendency to form silica on at least a surface thereof also is provided. The steel includes a near-surface region that has been depleted of silicon relative to a remainder of the steel.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A method of automated video device testing, and source and sink video devices are disclosed. A test signal may be provided by way of a video link from a video source to a video sink, over a video link extending therebetween. The method includes receiving on the video link a request from the video sink to provide the test signal; identifying based on the request, a requested test signal; providing the requested test signal from the video source to the video sink over the video link. In another embodiment, a video sink may be queried over a video link to determine a metric describing at least a portion of know video signal, as received and determined at the video sink to verify integrity of the video signal at the video sink.

Abstract: A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calculated tag distance is used to determine whether the pixels are outside a local image area defined about the uncached pixels. Pixels determined to be outside the local image area are replaced with the uncached pixels. The motion prediction cache can be organized as sets of cache lines and the method can be performed for each of the cache lines in one of the sets. The definition of the sets can be changed in response to cache performance. Similarly, the local image area can be redefined in response to cache performance.

Abstract: An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.

Abstract: A method of providing cipher data during a period of time when output of a primary source of cipher data is unavailable is disclosed. The method comprises switching from a primary source of cipher data to an alternate source of cipher data at a beginning of the period of time; using the cipher data from the alternate source during the period of time; and switching back to the primary source at an end of the period of time.

Abstract: A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an interrupt should be generated to service the event. A timer at the peripheral device is adjusted as needed to maintain a value within the acceptable period. Upon expiry of the timer a single interrupt is generated to a processor interconnected to the peripheral device. In response to the single interrupt, software code is executed on the processor to service un-serviced hardware events for which an indicator has been recorded.

Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: The optimized primitive filler is used in a computer system, such as a computer system that displays graphic images. A first step of the method it is determined if a primitive is totally outside a predetermined screen region or at least partially within the predetermined screen region. The primitive is then discarded if the primitive is totally outside the screen region. If the primitive is not totally outside the screen region, at least a portion of the primitive is identified that lies within the screen region. Then only those pixels in the portion of the primitive that is inside the screen region are filled. These steps are executed for each primitive of a plurality of primitives that forms a scene of which the screen region is the portion that the computer system displays. No pixels are filled in primitives which are totally outside the screen region, and no pixels are filled in portions of primitives that are outside the screen region.