Patents Assigned to ATI
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Patent number: 9041720Abstract: A circuit includes memory retiling methods which distribute image information among a plurality of memory channels producing reconfigured image information distributed among a subset of the plurality of memory channels allowing memory channels outside of the subset to be placed into a power save mode to reduce power consumption. Additional methods are disclosed for further reductions in power consumption.Type: GrantFiled: December 18, 2009Date of Patent: May 26, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Greg Sadowski, Warren Fritz Kruger, John Wakefield Brothers, III, David I.J. Glen, Stephen David Presant
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Patent number: 9035471Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.Type: GrantFiled: February 25, 2014Date of Patent: May 19, 2015Assignee: ATI Technologies ULCInventors: Roden Topacio, Gabriel Wong
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Publication number: 20150129093Abstract: A method of processing a metal alloy includes heating to a temperature in a working temperature range from a recrystallization temperature of the metal alloy to a temperature less than an incipient melting temperature of the metal alloy, and working the alloy. At least a surface region is heated to a temperature in the working temperature range. The surface region is maintained within the working temperature range for a period of time to recrystallize the surface region of the metal alloy, and the alloy is cooled so as to minimize grain growth. In embodiments including superaustenitic and austenitic stainless steel alloys, process temperatures and times are selected to avoid precipitation of deleterious intermetallic sigma-phase. A hot worked superaustenitic stainless steel alloy having equiaxed grains throughout the alloy is also disclosed.Type: ApplicationFiled: November 12, 2013Publication date: May 14, 2015Applicant: ATI PROPERTIES, INC.Inventors: Robin M. Forbes Jones, Ramesh S. Minisandram
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Patent number: 9027374Abstract: A method of processing an alloy workpiece to reduce thermal cracking may comprise spraying a metallic coating material onto at least a portion of a surface of the alloy workpiece to form a surface coating metallurgically bonded to the alloy workpiece. The surface coating may be more ductile than the alloy workpiece and reduces heat loss from the alloy workpiece.Type: GrantFiled: March 15, 2013Date of Patent: May 12, 2015Assignee: ATI Properties, Inc.Inventors: Robin M. Forbes Jones, Richard L. Kennedy, Wei-Di Cao
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Patent number: 9024682Abstract: A current generator includes first and second current generators and an output current generator. The first current generator has an output for providing a first current, the first current proportional to a difference between a first power supply voltage and a first gate-to-source voltage. The second current generator has an output for providing a second current, the second current proportional to a second gate-to-source voltage. The second gate-to-source voltage is approximately equal to the first gate-to-source voltage. The output current generator provides an output current proportional to a sum of said first current and said second current.Type: GrantFiled: August 27, 2013Date of Patent: May 5, 2015Assignee: ATI Technologies, ULCInventors: Boris Krnic, James Lin
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Publication number: 20150120978Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.Type: ApplicationFiled: October 24, 2014Publication date: April 30, 2015Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, Philip Ng, Maggie Chan, Vincent Cueva, Liang Chen, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien, Yaniv Adiri
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Patent number: 9020044Abstract: A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream.Type: GrantFiled: June 13, 2011Date of Patent: April 28, 2015Assignee: ATI Technologies ULCInventors: Lei Zhang, Benedict C. Chien, Edward A. Harold
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Patent number: 9021276Abstract: A method and device for setting a processor performance profile for a processor that is unable to directly measure voltage supplied by a voltage regulator includes determining a voltage requested of the voltage regulator and determining a first characteristic of a first portion of the electrical component. The first characteristic is one of power consumed by the first portion of the electrical component and load presented by the first portion of the electrical component. A first current is then determined by using the first voltage, the first characteristic, and a known relationship therebetween. A third voltage that is an estimate of the voltage supplied by the voltage regulator is then determined by comparing the first current to load line characteristics of the electrical component. The third voltage is then used to manage performance of the processor.Type: GrantFiled: May 7, 2012Date of Patent: April 28, 2015Assignee: ATI Technologies ULCInventors: Michael J. Osborn, Sebastien Nussbaum, John P. Petry, Umair B. Cheema
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Patent number: 9015357Abstract: A method and device for operating a data link having multiple data lanes is provided. The method includes supplying first data (such as video data that follows the DisplayPort protocol) on one or more data lanes of a data interface between a video source device and a video sink device. In addition to being video stream data (such as the above mentioned DisplayPort video data) the first data can also be audio stream data (such as DisplayPort audio data), source-sink interface configuration data (such as DisplayPort AUX data) and sink related interrupt data (such as DisplayPort Hot Plug Detect “HPD” data). The method also includes receiving second data on one or more unidirectional data lanes of the data interface. The second data being data other than video stream data, source-sink interface configuration data and sink related interrupt data.Type: GrantFiled: October 22, 2012Date of Patent: April 21, 2015Assignee: ATI Technologies ULCInventors: James D. Hunkins, Collis Quinn Carter
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Publication number: 20150106916Abstract: A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: David A. Kaplan, Philip Ng
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Patent number: 9009419Abstract: Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a CPU and an APD. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the CPU or the APD, and performing the memory instruction based on the mapping.Type: GrantFiled: July 31, 2012Date of Patent: April 14, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Asaro, Kevin Normoyle, Mark D. Hummel, Mark Fowler
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Patent number: 9008591Abstract: An apparatus and method is provided for improving initialization and synchronization of display devices to audio data. Current implementations to retain synchronization between a transmitter and a display use “Keep Alive” silent audio data stream in the format of the latest data stream on an interface between the transmitter and the display even when no data is available. Implementing the above solution in a system where the silent audio data stream is transmitted over a wireless link is bandwidth and power inefficient. The techniques provide an apparatus and method to efficiently generate and transmit silent audio data stream for maintaining synchronization.Type: GrantFiled: June 22, 2012Date of Patent: April 14, 2015Assignee: ATI Technologies ULCInventors: Gabriel Abarca, Keith Shu Key Lee
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Patent number: 9008148Abstract: A method for refining and casting metals and metal alloys includes melting and refining a metallic material and then casting the refined molten material by a nucleated casting technique. The refined molten material is provided to the atomizing nozzle of the nucleated casting apparatus through a transfer apparatus adapted to maintain the purity of the molten refined material. An apparatus including a melting and refining apparatus, a transfer apparatus, and a nucleated casting apparatus, in serial fluid communication, also is disclosed.Type: GrantFiled: November 28, 2006Date of Patent: April 14, 2015Assignee: ATI Properties, Inc.Inventors: Robin M. Forbes Jones, Richard L. Kennedy, Ramesh S. Minisandram
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Publication number: 20150098507Abstract: A motion estimation apparatus and method (carried out electronically) provides for encoding of multiview video, such as stereoscopic video, by providing motion estimation for pixels in a dependent eye view, using motion vector information from a colocated group of pixels in a base eye view and neighboring pixels to the colocated group of pixels in the base eye view. The method and apparatus encodes a group of pixels in a dependent eye view based on the estimated motion vector information. The method and apparatus may also include obtaining a frame of pixels that includes both base eye view pixels and dependent eye pixels so that, for example, frame compatible format packing can be employed. In one example, estimating the motion vector information for a block of pixels, for example, in a dependent eye view is based on a median value calculation of motion vectors for a block of pixels in a base eye view and motion vectors for neighboring blocks of pixels to the colocated group of pixels in the base eye view.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: ATI Technologies ULCInventor: Jiao Wang
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Publication number: 20150100818Abstract: A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log.Type: ApplicationFiled: October 3, 2013Publication date: April 9, 2015Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Andrew Kegel, Jimshed Mirza, Paul Blinzer, Philip Ng
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Patent number: 9001141Abstract: An apparatus and method for providing display information generates, independently from an operating system, different screen subsections of a screen image using independent gamut remapping configurations to generate an output image in a target gamut space of a display. The method and apparatus also provides the generated output image for display or may display the generated output image.Type: GrantFiled: September 24, 2012Date of Patent: April 7, 2015Assignee: ATI Technologies ULCInventors: David I. J. Glen, Jie Zhou
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Publication number: 20150092856Abstract: The present disclosure is directed a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network. The method and system of the present disclosure can be used in a server operating in a cloud gaming service to improve, for example, the amount of latency, downstream bandwidth, and/or computational processing power associated with playing a video game over its service. The method and system of the present disclosure can be further used in other applications where camera and depth information of a rendered or captured video frame is available.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Khaled MAMMOU, Ihab Amer, Sines Gabor, Lei Zhang, Michael Schmit, Daniel Wong
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Patent number: 8984322Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.Type: GrantFiled: May 1, 2012Date of Patent: March 17, 2015Assignee: ATI Technologies ULCInventors: Kevin D. Senohrabek, Natale Barbiero, Gordon F. Caruk
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Patent number: 8984192Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.Type: GrantFiled: October 29, 2012Date of Patent: March 17, 2015Assignee: ATI Technologies ULCInventors: Natale Barbiero, Gordon F. Caruk
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Patent number: 8984511Abstract: Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.Type: GrantFiled: August 17, 2012Date of Patent: March 17, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Asaro, Kevin Normoyle, Mark Hummel