Abstract: Provided herein is a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal.

Abstract: A method of forming an article from an ?-? titanium including, in weight percentages, from about 2.9 to about 5.0 aluminum, from about 2.0 to about 3.0 vanadium, from about 0.4 to about 2.0 iron, from about 0.2 to about 0.3 oxygen, from about 0.005 to about 0.3 carbon, from about 0.001 to about 0.02 nitrogen, and less than about 0.5 of other elements. The method comprises cold working the ?-? titanium alloy.

Abstract: A method of forming an article from an ??? titanium including, in weight percentages, from about 2.9 to about 5.0 aluminum, from about 2.0 to about 3.0 vanadium, from about 0.4 to about 2.0 iron, from about 0.2 to about 0.3 oxygen, from about 0.005 to about 0.3 carbon, from about 0.001 to about 0.02 nitrogen, and less than about 0.5 of other elements. The method comprises cold working the ??? titanium alloy.

Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.

Abstract: A power adjustment circuit includes memory controller logic that is couplable to system memory or other memory if desired. The memory control logic is operative to provide a variable memory clock signal to the system memory and to place the system memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal. Thereafter, the memory clock control logic adjusts the frequency of the memory clock signal to a lower (or higher) frequency clock signal, and in response to the frequency of the memory clock signal becoming stable, the memory clock control logic restores the memory to a normal mode using the lower adjusted frequency memory clock signal. As such, a dynamic memory clock switching mechanism is employed for quickly varying the frequency of memory modules for discrete graphics processors, graphics processors integrated on a chip, or any other processors such that the memory clock can be reduced to a lower frequency in real time to save power.

Abstract: A method for making a ferritic stainless steel article having an oxidation resistant surface includes providing a ferritic stainless steel comprising aluminum, at least one rare earth metal and 16 to less than 30 weight percent chromium, wherein the total weight of rare earth metals is greater than 0.02 weight percent. At least one surface of the ferritic stainless steel is modified so that, when subjected to an oxidizing atmosphere at high temperature, the modified surface develops an electrically conductive, aluminum-rich, oxidation resistant oxide scale comprising chromium and iron and a having a hematite structure differing from Fe2O3, alpha Cr2O3 and alpha Al2O3. The modified surface may be provided, for example, by electrochemically modifying the surface, such as by electropolishing the surface.

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronizaiton, transmitter/receiver synchronization or for other control signalling.

Abstract: A method for determining a macroblock (MB) coding mode for a current MB in a dependent view. A window around a co-located MB in a base view is determined, wherein the co-located MB is a MB in the base view having a same location as the current MB in the dependent view. A coding mode complexity value (CMCV) is determined for each MB in the window, wherein the CMCV is based on a coding mode used to encode the MB. Rate distortion optimization (RDO) is performed for the current MB using a reduced number of coding modes if a total CMCV for all MBs in the window is less than a threshold, or using all supported coding modes if the total CMCV for all MBs in the window is greater than the threshold. A coding mode for the current MB is determined based on the RDO results.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.

Abstract: A method apparatus for automated display video programming guide information includes filtering programming information using filtering rules to determine viewing events of interest to a user. The method and apparatus further includes displaying on a first screen portion, the viewing events in a chronological order based on a display time for each of the viewing events. The method and apparatus further includes displaying a selector in the first screen portion such that the selector is operative to select one of the viewing events and displaying on a second screen portion, event information relating to a selected one of the plurality viewing events when the selector is proximate to one of the viewing events. The method and apparatus further includes resolving a scheduling conflict between a first viewing event and second viewing event to generate a list of program guide information.

Abstract: In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: Metastable beta titanium alloys and methods of processing metastable ?-titanium alloys are disclosed. For example, certain non-limiting embodiments relate to metastable ?-titanium alloys, such as binary ?-titanium alloys comprising greater than 10 weight percent molybdenum, having tensile strengths of at least 150 ksi and elongations of at least 12 percent. Other non-limiting embodiments relate to methods of processing metastable ?-titanium alloys, and more specifically, methods of processing binary ?-titanium alloys comprising greater than 10 weight percent molybdenum, wherein the method comprises hot working and direct aging the metastable ?-titanium alloy at a temperature below the ?-transus temperature of the metastable ?-titanium alloy for a time sufficient to form ?-phase precipitates in the metastable ?-titanium alloy. Articles of manufacture comprising binary ?-titanium alloys according to various non-limiting embodiments disclosed herein are also disclosed.

Abstract: An apparatus for melting an electrically conductive metallic material includes a vacuum chamber and a hearth disposed in the vacuum chamber. At least one wire-discharge ion plasma electron emitter is disposed in or adjacent the vacuum chamber and is positioned to direct a wide-area field of electrons into the vacuum chamber, wherein the wide-area electron field has sufficient energy to heat the electrically conductive metallic material to its melting temperature. The apparatus may further include at least one of a mold and an atomizing apparatus which is in communication with the vacuum chamber and is positioned to receive molten material from the hearth.

Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.

Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.

Abstract: Processes for producing a nickel-titanium alloy are disclosed. The processes are characterized by the production of nickel-titanium alloy articles having improved microstructure. A pre-alloyed nickel-titanium alloy is melted and atomized to form molten nickel-titanium alloy particles. The molten nickel-titanium alloy particles are cooled to form nickel-titanium alloy powder. The nickel-titanium alloy powder is consolidated to form a fully-densified nickel-titanium alloy preform that is hot worked to form a nickel-titanium alloy article. Any second phases present in the nickel-titanium alloy article have a mean size of less than 10 micrometers measured according to ASTM E1245-03 (2008) or an equivalent method.

Abstract: A method of reducing the formation of electrically resistive scale on a an article comprising a silicon-containing ferritic stainless subjected to oxidizing conditions in service includes, prior to placing the article in service, subjecting the article to conditions under which silica, which includes silicon derived from the steel, forms on a surface of the steel. Optionally, at least a portion of the silica is removed from the surface to placing the article in service. A ferritic stainless steel alloy having a reduced tendency to form silica on at least a surface thereof also is provided. The steel includes a near-surface region that has been depleted of silicon relative to a remainder of the steel.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.