Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: The present invention is directed to a method, computer program product, and system for performing physics simulations on at least one graphics processor unit (GPU). The method includes the following steps. First, data representing physical attributes associated with at least one mesh are mapped into a plurality of memory arrays to set up of a linear system of equations that governs motion of the at least one mesh depicted in a scene. Then, computations are performed on the data in the plurality of memory arrays using at least one pixel processor to solve the linear system of equations for an instant of time, wherein modified data representing the solution to the linear system of equations for the instant of time are stored in the plurality of memory arrays.

Abstract: A method for reducing impurities in magnesium comprises: combining a zirconium-containing material with a molten low-impurity magnesium including no more than 1.0 weight percent of total impurities in a vessel to provide a mixture; holding the mixture in a molten state for a period of time sufficient to allow at least a portion of the zirconium-containing material to react with at least a portion of the impurities and form intermetallic compounds; and separating at least a portion of the molten magnesium in the mixture from at least a portion of the intermetallic compounds to provide a purified magnesium including greater than 1000 ppm zirconium. A purified magnesium including at least 1000 ppm zirconium and methods for producing zirconium metal using magnesium reductant also are disclosed.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A thermo-mechanical treatment process is disclosed. A nickel-base alloy workpiece is heated in a first heating step to a temperature greater than the M23C6 carbide solvus temperature of the nickel-base alloy. The nickel-base alloy workpiece is worked in a first working step to a reduction in area of 20% to 70%. The nickel-base alloy workpiece is at a temperature greater than the M23C6 carbide solvus temperature when the first working step begins. The nickel-base alloy workpiece is heated in a second working step to a temperature greater than 1700° F. (926° C.) and less than the M23C6 carbide solvus temperature of the nickel-base alloy. The nickel-base alloy workpiece is not permitted to cool to ambient temperature between completion of the first working step and the beginning of the second heating step. The nickel-base alloy workpiece is worked to a second reduction in area of 20% to 70%. The nickel-base alloy workpiece is at a temperature greater than 1700° F. (926° C.

Abstract: A system includes a power management unit that may be configured to estimate the power consumed by at least a portion of each of one or more processor cores during operation of each processor core. The power management unit may be configured to generate a sum of activity values and normal weight factor values for a predetermined set of signals within each processor core to estimate the power consumed. The power management unit may also be configured to adaptively generate and selectively use new weight factor values to estimate the power consumed based upon a total measured dynamic power consumed by each processor core during operation.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract: A method and apparatus for video stream processing is implemented in a monitor scaler chip (MSC). The MSC receives the video stream and determines whether the video stream includes copy protected content. The MSC routes the video stream based upon the determination.

Abstract: The present method and system enables receiving a radio frequency (RF) signal. The received RF signal is assigned to a single instruction multiple data (SIMD) module in an accelerated processing device (APD) for processing to extract network messages. The extracted network layer messages are further processed by the SIMD module to obtain data transmitted via the RF signal.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: An apparatus for melting an electrically conductive metallic material includes a vacuum chamber and a hearth disposed in the vacuum chamber. At least one wire-discharge ion plasma electron emitter is disposed in or adjacent the vacuum chamber and is positioned to direct a wide-area field of electrons into the vacuum chamber, wherein the wide-area electron field has sufficient energy to heat the electrically conductive metallic material to its melting temperature. The apparatus may further include at least one of a mold and an atomizing apparatus which is in communication with the vacuum chamber and is positioned to receive molten material from the hearth.

Abstract: A digital rights management system includes an authentication module and a decryption module. If desired, the modules can be implemented in separate integrated circuits. The authentication module retrieves authentication information for protected content and powers down after the authentication information is retrieved. The decryption module decrypts the protected content based on the authentication information while the authentication module is powered down.

Abstract: A device may generate a clock signal using spread-spectrum clocking. The spread-spectrum clocking may modulate a frequency of the clock signal to produce a plurality of frequencies for the clock signal during a modulation cycle. The device may receive an instruction to disable the spread-spectrum clocking, and may disable the spread spectrum clocking at the end of the modulation cycle.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

Abstract: A method and apparatus provide for improving signal quality. The method includes receiving a first media signal, such as a video signal, in a first format, such as 1080p. The provided video signal is one that is created by upsampling a video signal recorded in a format having a lower sampling rate. The method also includes obtaining a second signal indicative of error within the first media signal. The second signal is in a second format, such as the format having a lower sampling rage in which the video signal was recorded. The signal is processed to place the second signal in the format of the first signal. Then, the estimated error signal is combined with the original signal to arrive at an error corrected output.